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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b6nRAODSj3A+njpmEvkKG6MZDCxoqpBC7OBUkW09dQw=; b=Dm91mEnTKO40yVZECepwOevFnZucSkWmooWqfOnIkpX9a1/vzU8Oy+ud7N7ezr5jBz u2eqJz5GQgkKQMuOPpNm9lCZFuoQxXnLj+U9/+vGdDNyENaMEoeh5xMSw55vNgFUBtpZ 8wg8h1dwLe/+COYcCNhC1d95fymUR2pXk4FIw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b6nRAODSj3A+njpmEvkKG6MZDCxoqpBC7OBUkW09dQw=; b=aP1wFh0p4uOCuLRWmi1TKW53P86Lz1B7ceap23DDGrhVQNxYD++H9I5BaSzDtZq1Oj nIHX0Iaj1TUBoCbaZWpyRSwoq3a3JuW7O/XOBPGUmrdQmcGhq89Vmh4mQtZORrqBWvqY Q8mpzrLsKw/ubyXYgKmaVf92b0E6ac3Hb8dvZnvF5get6/BlyMcFM1WespjKBPfmjULo KjndRySERcD3PirfUG0VTW3DAuwPFdedVSkVJ3WHw3qkYVtBGfQPk2Of5d+Wdo2AD3cC FNtZYon0w0RmQK6WwALUEb0FfaGrpTJEuz3mXGXTzGvLSQddXGleTN8vuFnRv+G499OQ WT8w== X-Gm-Message-State: APzg51AaPw00Xm07zG2C/EAbDOVJ3Jf9O+DjQWsD6HXCXtEetK9VOrbC ih90UgT4FtXOAsFe1QUsfk23woGLk0I= X-Google-Smtp-Source: ANB0VdZpDNqF70AknDx/iSMsBye2GLMrjniR5MmRhmhrJJXtHACg2wXwuj+8JJjuDVO+bs+i9NHpqQ== X-Received: by 2002:a63:a619:: with SMTP id t25-v6mr16514274pge.288.1537028270562; Sat, 15 Sep 2018 09:17:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:32 -0700 Message-Id: <20180915161738.25257-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 07/13] target/arm: Derive id_isar5 and id_isar6 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Unlike the other id_sar registers, these contain post-v8.0 features that are not included with any existing cpu models. They would be enabled by -cpu max when we enable them for system mode. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3c6ddd6532..c227044946 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -926,6 +926,49 @@ static uint32_t resolve_id_isar4(CPUARMState *env) return ret; } =20 +static uint32_t resolve_id_isar5(CPUARMState *env) +{ + uint32_t ret =3D 0; + + /* SEVL -- we always implement as NOP. */ + /* AES */ + if (arm_feature(env, ARM_FEATURE_V8_PMULL)) { + ret =3D deposit32(ret, 4, 4, 2); + } else if (arm_feature(env, ARM_FEATURE_V8_AES)) { + ret =3D deposit32(ret, 4, 4, 1); + } + if (arm_feature(env, ARM_FEATURE_V8_SHA1)) { + ret =3D deposit32(ret, 8, 4, 1); /* SHA1 */ + } + if (arm_feature(env, ARM_FEATURE_V8_SHA256)) { + ret =3D deposit32(ret, 12, 4, 1); /* SHA2 */ + } + if (arm_feature(env, ARM_FEATURE_CRC)) { + ret =3D deposit32(ret, 16, 4, 1); /* CRC32 */ + } + if (arm_feature(env, ARM_FEATURE_V8_RDM)) { + ret =3D deposit32(ret, 24, 4, 1); /* RDM */ + } + if (arm_feature(env, ARM_FEATURE_V8_FCMA)) { + ret =3D deposit32(ret, 28, 4, 1); /* VCMA */ + } + + return ret; +} + +static uint32_t resolve_id_isar6(CPUARMState *env) +{ + uint32_t ret =3D 0; + + /* JSCVT -- not implemented yet */ + /* FHM -- not implemented yet */ + if (arm_feature(env, ARM_FEATURE_V8_DOTPROD)) { + ret =3D deposit32(ret, 4, 4, 1); /* DP */ + } + + return ret; +} + static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; @@ -951,6 +994,9 @@ static void resolve_id_regs(ARMCPU *cpu) cpu->id_isar4 =3D resolve_id_isar4(env); /* Willfully ignore the SWP_frac field. */ g_assert_cmphex(cpu->id_isar4 & 0x0fffffff, =3D=3D, orig & 0x0fffffff); + + cpu->id_isar5 =3D resolve_id_isar5(env); + cpu->id_isar6 =3D resolve_id_isar6(env); } =20 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) --=20 2.17.1