From nobody Fri Nov 7 09:09:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15370285804100.9369624639917902; Sat, 15 Sep 2018 09:23:00 -0700 (PDT) Received: from localhost ([::1]:56116 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g1DLX-0000Iv-2G for importer@patchew.org; Sat, 15 Sep 2018 12:22:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60157) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g1DGZ-0004Vb-E8 for qemu-devel@nongnu.org; Sat, 15 Sep 2018 12:17:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g1DGY-0003wt-5W for qemu-devel@nongnu.org; Sat, 15 Sep 2018 12:17:51 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:41796) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g1DGW-0003uV-8Q for qemu-devel@nongnu.org; Sat, 15 Sep 2018 12:17:49 -0400 Received: by mail-pg1-x530.google.com with SMTP id s15-v6so5749458pgv.8 for ; Sat, 15 Sep 2018 09:17:47 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8tq7ljLEg+ZEL7FdvFxOiLdkjOjupm3VfXgk7BqhQxQ=; b=IMwrJE7wwr2qSvfzT8rBltBm4E1azbnZx53rG0mZLyzLTERlvG46DK50Y/n2t5w6lE kJMbpGLjxw/mTJDRYn6RyEAVfpHzKSadvnOr9daIpfjZ7oNIZNLThVQwoqiMXc0TVsOi qdc0szoG48W1zpbIAI9XzxW1og1Quwr6Bxy14= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8tq7ljLEg+ZEL7FdvFxOiLdkjOjupm3VfXgk7BqhQxQ=; b=SQ0gUaQMRGUZZCRjavFroegcoeii18XwEOXez81p2nG5dsnyWMMoVXj6g8U0mHduaG hOSYRRsViS2JUKurt3NE5oLTmbAGyp/yyFr3ulQPRHoZivJ36tJmMrXNZqr4OslxssWi jCJZhEDHgs5ZhI4U6LN1TOevz2c0V7VTUuhIAgzgCW0cQVfGZ45YB/p/kn0pEGyhm6n9 ms5Cr8JXMDw9R/aH3hIrKEerUTvmRBYeLL1wjaZIV3EAg6CLLm7ZZiMDvtePy13SMfYR qBYqwconztdcGOl6eOphhv/Y77cEZY9ShkbCDncczIkrdm7YmJvNaQxQnTN18Lmmw3Mf UdLQ== X-Gm-Message-State: APzg51CXv6u8d74fBKk2+jensolnj4HAMesCvj9A470B0u/RZcq9w5hU Zpa7OLXaId3ll9N9ChYq8gYjyQ8qOY8= X-Google-Smtp-Source: ANB0VdZDw6h9B1g0xtzmSoOijHAuUaNmI1R/7kLMg3lJ0axbHvil4WAm9ml34Fo+JW0sVHMuua4u2g== X-Received: by 2002:aa7:818f:: with SMTP id g15-v6mr17920249pfi.71.1537028266511; Sat, 15 Sep 2018 09:17:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:29 -0700 Message-Id: <20180915161738.25257-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::530 Subject: [Qemu-devel] [PATCH 04/13] target/arm: Derive id_isar2 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" ??? The assertion does fire for the old cpus; they may be existing bugs. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a477e722af..379d6a08a4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -821,6 +821,40 @@ static uint32_t resolve_id_isar1(CPUARMState *env) return ret; } =20 +static uint32_t resolve_id_isar2(CPUARMState *env, uint32_t orig) +{ + uint32_t ret =3D 0; + + /* LoadStore */ + ret =3D deposit32(ret, 0, 4, + arm_feature(env, ARM_FEATURE_V8) ? 2 : + arm_feature(env, ARM_FEATURE_V5) ? 1 : 0); + /* + * MemHint -- v7mp has pldw (4), v7 has pli (3), but values 1 & 2 + * mean the same thing, and there does not seem to be a way to tell + * them apart for v5 & v6. + */ + ret |=3D orig & MAKE_64BIT_MASK(4, 4); + /* MultiAccessInt -- micro-architectural detail. */ + ret |=3D orig & MAKE_64BIT_MASK(8, 4); + /* Mult -- note we don't support pre-armv4t. */ + ret =3D deposit32(ret, 12, 4, arm_feature(env, ARM_FEATURE_THUMB2) ? 2= : 1); + /* MultS -- note we don't support pre-armv4t. */ + ret =3D deposit32(ret, 16, 4, + arm_feature(env, ARM_FEATURE_V6) ? 3 : + arm_feature(env, ARM_FEATURE_V5) ? 2 : 1); + /* MultU -- note we don't support pre-armv4t. */ + ret =3D deposit32(ret, 20, 4, arm_feature(env, ARM_FEATURE_V6) ? 2 : 1= ); + /* PSR_AR */ + ret =3D deposit32(ret, 24, 4, arm_feature(env, ARM_FEATURE_M) ? 0 : 1); + /* Reversal */ + ret =3D deposit32(ret, 28, 4, + arm_feature(env, ARM_FEATURE_THUMB2) ? 2 : + arm_feature(env, ARM_FEATURE_V6) ? 1 : 0); + + return ret; +} + static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; @@ -833,6 +867,10 @@ static void resolve_id_regs(ARMCPU *cpu) orig =3D cpu->id_isar1; cpu->id_isar1 =3D resolve_id_isar1(env); g_assert_cmphex(cpu->id_isar1, =3D=3D, orig); + + orig =3D cpu->id_isar2; + cpu->id_isar2 =3D resolve_id_isar2(env, orig); + g_assert_cmphex(cpu->id_isar2, =3D=3D, orig); } =20 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) --=20 2.17.1