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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jgmkTEluYq/Qp7SO+CS3JMwIujLwX/BOHR5l9U0Ukbw=; b=ary9sSbH8ZGW182aHqLzYAQ1LEITJbii3BQUuD6SguZ64wesaGRMC0t6SiXqdtAsgY b9yt5O4ZPBhGVGjrpDdZRNseY7eJGpKRbVMW9X0ahPAjp4yhZc+N4//KUruGjMRBc/S2 JaF9nOq+ySKndSPYjs+42l4/ORo0XBbmiQ6cI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jgmkTEluYq/Qp7SO+CS3JMwIujLwX/BOHR5l9U0Ukbw=; b=dIey33tjKur4PSn67gwkti63w7rzfy/9U3AN93cEciavgNFka6kWlQNVHo9jBEeT/V S7xPGLIg0WbO1lwGo8DyerqvzHsRaAZwjNOH+JOf76L5E1s+QJFXOsTR4FqZiULtNgcA OIURXektYZ4HwAQRWOele4+EwyKMGqqp1kvmNSXK1NEMcN/teAMZP4XXlpXlNf8xyfEm KKbBrwLpejwgP3zqyC43OmPucGVRwpJ9iwyYhzIJMruvM3WUmWqvj/1h9+crFjdHJQbA Rd6dY6yom/GrMoXtvb67AilF2NmhVxSy2r6feQMJ3raP+/DL9m8wnUXMYbSNj2cm6pOK Up1A== X-Gm-Message-State: APzg51A56cvzuEHBfMwnc43cMdCgy4ov5YJaF6NwejB8dRcyCqFvr1FJ d0YBeqk0y/FztUyBvrZ4KBxnNKtkBRA= X-Google-Smtp-Source: ANB0VdZaVXfh7Cf5Jd9i3omvLIEII69knzikkQ5rGe/Kh4fnLpmQJVFsDHUX4SxI0Mkzpc2CTBC4cA== X-Received: by 2002:a63:3cc:: with SMTP id 195-v6mr16189011pgd.229.1537028274634; Sat, 15 Sep 2018 09:17:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:35 -0700 Message-Id: <20180915161738.25257-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::433 Subject: [Qemu-devel] [PATCH 10/13] target/arm: Derive id_aa64isar0 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4fb3e0a9ea..1c51b9f631 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1017,6 +1017,51 @@ static uint32_t resolve_id_pfr1(CPUARMState *env) return ret; } =20 +static uint64_t resolve_id_aa64isar0(CPUARMState *env) +{ + uint64_t ret =3D 0; + + /* AES */ + if (arm_feature(env, ARM_FEATURE_V8_PMULL)) { + ret =3D deposit64(ret, 4, 4, 2); + } else if (arm_feature(env, ARM_FEATURE_V8_AES)) { + ret =3D deposit64(ret, 4, 4, 1); + } + if (arm_feature(env, ARM_FEATURE_V8_SHA1)) { + ret =3D deposit64(ret, 8, 4, 1); /* SHA1 */ + } + /* SHA2 */ + if (arm_feature(env, ARM_FEATURE_V8_SHA512)) { + ret =3D deposit64(ret, 12, 4, 2); + } else if (arm_feature(env, ARM_FEATURE_V8_SHA256)) { + ret =3D deposit64(ret, 12, 4, 1); + } + if (arm_feature(env, ARM_FEATURE_CRC)) { + ret =3D deposit64(ret, 16, 4, 1); /* CRC32 */ + } + if (arm_feature(env, ARM_FEATURE_V8_ATOMICS)) { + ret =3D deposit64(ret, 20, 4, 2); /* Atomic */ + } + if (arm_feature(env, ARM_FEATURE_V8_RDM)) { + ret =3D deposit64(ret, 28, 4, 1); /* RDM */ + } + if (arm_feature(env, ARM_FEATURE_V8_SHA3)) { + ret =3D deposit64(ret, 32, 4, 1); /* SHA3 */ + } + if (arm_feature(env, ARM_FEATURE_V8_SM3)) { + ret =3D deposit64(ret, 36, 4, 1); /* SM3 */ + } + if (arm_feature(env, ARM_FEATURE_V8_SM4)) { + ret =3D deposit64(ret, 40, 4, 1); /* SM4 */ + } + if (arm_feature(env, ARM_FEATURE_V8_DOTPROD)) { + ret =3D deposit64(ret, 44, 4, 1); /* DP */ + } + /* FHM -- not implemented yet */ + + return ret; +} + static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; @@ -1053,6 +1098,10 @@ static void resolve_id_regs(ARMCPU *cpu) orig =3D cpu->id_pfr1; cpu->id_pfr1 =3D resolve_id_pfr1(env); g_assert_cmphex(cpu->id_pfr1, =3D=3D, orig); + + orig =3D cpu->id_aa64isar0; + cpu->id_aa64isar0 =3D resolve_id_aa64isar0(env); + g_assert_cmphex(cpu->id_aa64isar0, =3D=3D, orig); } =20 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) --=20 2.17.1