From nobody Wed Nov 5 20:17:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1536622939630954.9233461429573; Mon, 10 Sep 2018 16:42:19 -0700 (PDT) Received: from localhost ([::1]:54628 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fzVow-0000MA-J6 for importer@patchew.org; Mon, 10 Sep 2018 19:42:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40237) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fzVjt-0003UC-6n for qemu-devel@nongnu.org; Mon, 10 Sep 2018 19:37:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fzVbR-0005Ie-Vo for qemu-devel@nongnu.org; Mon, 10 Sep 2018 19:28:25 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:59675) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fzVbR-0005HW-MP for qemu-devel@nongnu.org; Mon, 10 Sep 2018 19:28:21 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id AB5CC21E0D; Mon, 10 Sep 2018 19:28:20 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Mon, 10 Sep 2018 19:28:20 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 176FAE4682; Mon, 10 Sep 2018 19:28:20 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=mesmtp; bh=3KQXkycV9Q+hxa ei3kzwo8q73IONVzUGcLsW7OmlfWQ=; b=BmAD5l0XlD/bjxfYL6zrevYK/OqS1P DaoRm4bKLE18JvnbQmqXZhLf762y36y3cK1FqCyyoDmkrH4iEtXqb7HhYvJAjLKD q5+ScbhjCMVA8ChY0Q2Z+385TdgOyhveZR7CfvO7uPnWguYEWUA5FAiKyOodBojU +ZiYwIEYwBOhI= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=3KQXkycV9Q+hxaei3kzwo8q73IONVzUGcLsW7OmlfWQ=; b=ghhrv0WL yzz3hvYAxnj2KRxQ+sOii+IJJirZuANF2ysd7oKqoWSrCeBaeJ6aOlRk7hsj57pD jsEWWUztNqvCXWFShTF0o1C8la9LQ4xnvrHxXRcr9dThqbF0nrLc+qyB70P9DoK/ CD55x30Ng3bc6YKk3GyFzcVMy2arFj8kRzDB4Ey69N3Fe5tpVXfCeXvoyX1oMtmx dWsLSOZfdyHHL0DLlXKl6xhepWTGc0Pd0A7FVbq84mTMySt5KSuT7jlSaRakD21i 8ovktxiQYT2Q1HyD6jcoR0aY4FB7B2fwzr3vtF2zKqdsBu7DOQGSNQkU4XqljL9X THuju24ANbjT4w== X-ME-Proxy: X-ME-Sender: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Mon, 10 Sep 2018 19:27:42 -0400 Message-Id: <20180910232752.31565-3-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180910232752.31565-1-cota@braap.org> References: <20180910232752.31565-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 02/12] util: add atomic64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , Murilo Opsfelder Araujo , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This introduces read/set accessors for int64_t and uint64_t. Signed-off-by: Emilio G. Cota --- include/qemu/atomic.h | 34 ++++++++++++++++++ util/atomic64.c | 83 +++++++++++++++++++++++++++++++++++++++++++ util/cacheinfo.c | 3 ++ util/Makefile.objs | 1 + 4 files changed, 121 insertions(+) create mode 100644 util/atomic64.c diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h index 9ed39effd3..c34c2f78c4 100644 --- a/include/qemu/atomic.h +++ b/include/qemu/atomic.h @@ -450,4 +450,38 @@ _oldn; \ }) =20 +/* Abstractions to access atomically (i.e. "once") i64/u64 variables */ +#ifdef CONFIG_ATOMIC64 +static inline int64_t atomic_read_i64(const int64_t *ptr) +{ + /* use __nocheck because sizeof(void *) might be < sizeof(u64) */ + return atomic_read__nocheck(ptr); +} + +static inline uint64_t atomic_read_u64(const uint64_t *ptr) +{ + return atomic_read__nocheck(ptr); +} + +static inline void atomic_set_i64(int64_t *ptr, int64_t val) +{ + atomic_set__nocheck(ptr, val); +} + +static inline void atomic_set_u64(uint64_t *ptr, uint64_t val) +{ + atomic_set__nocheck(ptr, val); +} + +static inline void atomic64_init(void) +{ +} +#else /* !CONFIG_ATOMIC64 */ +int64_t atomic_read_i64(const int64_t *ptr); +uint64_t atomic_read_u64(const uint64_t *ptr); +void atomic_set_i64(int64_t *ptr, int64_t val); +void atomic_set_u64(uint64_t *ptr, uint64_t val); +void atomic64_init(void); +#endif /* !CONFIG_ATOMIC64 */ + #endif /* QEMU_ATOMIC_H */ diff --git a/util/atomic64.c b/util/atomic64.c new file mode 100644 index 0000000000..b198a6c9c8 --- /dev/null +++ b/util/atomic64.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2018, Emilio G. Cota + * + * License: GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ +#include "qemu/osdep.h" +#include "qemu/atomic.h" +#include "qemu/thread.h" + +#ifdef CONFIG_ATOMIC64 +#error This file must only be compiled if !CONFIG_ATOMIC64 +#endif + +/* + * When !CONFIG_ATOMIC64, we serialize both reads and writes with spinlock= s. + * We use an array of spinlocks, with padding computed at run-time based on + * the host's dcache line size. + * We point to the array with a void * to simplify the padding's computati= on. + * Each spinlock is located every lock_size bytes. + */ +static void *lock_array; +static size_t lock_size; + +/* + * Systems without CONFIG_ATOMIC64 are unlikely to have many cores, so we = use a + * small array of locks. + */ +#define NR_LOCKS 16 + +static QemuSpin *addr_to_lock(const void *addr) +{ + uintptr_t a =3D (uintptr_t)addr; + uintptr_t idx; + + idx =3D a >> qemu_dcache_linesize_log; + idx ^=3D (idx >> 8) ^ (idx >> 16); + idx &=3D NR_LOCKS - 1; + return lock_array + idx * lock_size; +} + +#define GEN_READ(name, type) \ + type name(const type *ptr) \ + { \ + QemuSpin *lock =3D addr_to_lock(ptr); \ + type ret; \ + \ + qemu_spin_lock(lock); \ + ret =3D *ptr; \ + qemu_spin_unlock(lock); \ + return ret; \ + } + +GEN_READ(atomic_read_i64, int64_t) +GEN_READ(atomic_read_u64, uint64_t) +#undef GEN_READ + +#define GEN_SET(name, type) \ + void name(type *ptr, type val) \ + { \ + QemuSpin *lock =3D addr_to_lock(ptr); \ + \ + qemu_spin_lock(lock); \ + *ptr =3D val; \ + qemu_spin_unlock(lock); \ + } + +GEN_SET(atomic_set_i64, int64_t) +GEN_SET(atomic_set_u64, uint64_t) +#undef GEN_SET + +void atomic64_init(void) +{ + int i; + + lock_size =3D ROUND_UP(sizeof(QemuSpin), qemu_dcache_linesize); + lock_array =3D qemu_memalign(qemu_dcache_linesize, lock_size * NR_LOCK= S); + for (i =3D 0; i < NR_LOCKS; i++) { + QemuSpin *lock =3D lock_array + i * lock_size; + + qemu_spin_init(lock); + } +} diff --git a/util/cacheinfo.c b/util/cacheinfo.c index 57c7d58159..6c6cbdb25d 100644 --- a/util/cacheinfo.c +++ b/util/cacheinfo.c @@ -8,6 +8,7 @@ =20 #include "qemu/osdep.h" #include "qemu/host-utils.h" +#include "qemu/atomic.h" =20 int qemu_icache_linesize =3D 0; int qemu_icache_linesize_log; @@ -179,4 +180,6 @@ static void __attribute__((constructor)) init_cache_inf= o(void) qemu_icache_linesize_log =3D 31 - clz32(isize); qemu_dcache_linesize =3D dsize; qemu_dcache_linesize_log =3D 31 - clz32(dsize); + + atomic64_init(); } diff --git a/util/Makefile.objs b/util/Makefile.objs index 0e88899011..0820923c18 100644 --- a/util/Makefile.objs +++ b/util/Makefile.objs @@ -3,6 +3,7 @@ util-obj-y +=3D bufferiszero.o util-obj-y +=3D lockcnt.o util-obj-y +=3D aiocb.o async.o aio-wait.o thread-pool.o qemu-timer.o util-obj-y +=3D main-loop.o iohandler.o +util-obj-$(call lnot,$(CONFIG_ATOMIC64)) +=3D atomic64.o util-obj-$(CONFIG_POSIX) +=3D aio-posix.o util-obj-$(CONFIG_POSIX) +=3D compatfd.o util-obj-$(CONFIG_POSIX) +=3D event_notifier-posix.o --=20 2.17.1