From nobody Wed Nov 5 10:15:13 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1536585692580794.6819887466897; Mon, 10 Sep 2018 06:21:32 -0700 (PDT) Received: from localhost ([::1]:51675 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fzM86-0004ah-KC for importer@patchew.org; Mon, 10 Sep 2018 09:21:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42680) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fzM49-0008Bz-NQ for qemu-devel@nongnu.org; Mon, 10 Sep 2018 09:17:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fzLrX-00036P-Au for qemu-devel@nongnu.org; Mon, 10 Sep 2018 09:04:23 -0400 Received: from mx2.suse.de ([195.135.220.15]:40204 helo=mx1.suse.de) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fzLrU-00030C-Iy for qemu-devel@nongnu.org; Mon, 10 Sep 2018 09:04:18 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id EA55AAEB2; Mon, 10 Sep 2018 13:04:12 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Johannes Thumshirn To: qemu-devel@nongnu.org Date: Mon, 10 Sep 2018 15:04:05 +0200 Message-Id: <20180910130407.24981-3-jthumshirn@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20180910130407.24981-1-jthumshirn@suse.de> References: <20180910130407.24981-1-jthumshirn@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x (no timestamps) [generic] X-Received-From: 195.135.220.15 Subject: [Qemu-devel] [RESEND PATCH v2 2/4] Add MEN Chameleon Bus via PCI carrier X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Johannes Thumshirn Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Johannes Thumshirn --- hw/mcb/Makefile.objs | 1 + hw/mcb/mcb-pci.c | 305 +++++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 306 insertions(+) create mode 100644 hw/mcb/mcb-pci.c diff --git a/hw/mcb/Makefile.objs b/hw/mcb/Makefile.objs index 32427c987c44..125f4a84700a 100644 --- a/hw/mcb/Makefile.objs +++ b/hw/mcb/Makefile.objs @@ -1 +1,2 @@ common-obj-$(CONFIG_MCB) +=3D mcb.o +common-obj-$(CONFIG_MCB) +=3D mcb-pci.o diff --git a/hw/mcb/mcb-pci.c b/hw/mcb/mcb-pci.c new file mode 100644 index 000000000000..a1a47980766f --- /dev/null +++ b/hw/mcb/mcb-pci.c @@ -0,0 +1,305 @@ +/* + * QEMU MEN Chameleon Bus emulation + * + * Copyright (C) 2016 - 2018 Johannes Thumshirn + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/mcb/mcb.h" +#include "hw/pci/pci.h" + +/* #define DEBUG_MPCI 1 */ + +#ifdef DEBUG_MPCI +#define DPRINTF(fmt, ...) \ + do { fprintf(stderr, "mcb-pci: " fmt, ## __VA_ARGS__); } while (0) +#else +#define DPRINTF(fmt, ...) do { } while (0) +#endif + +typedef struct { + uint8_t revision; + char model; + uint8_t minor; + uint8_t bus_type; + uint16_t magic; + uint16_t reserved; + /* This one has no '\0' at the end!!! */ + char filename[12]; +} ChameleonFPGAHeader; +#define CHAMELEON_BUS_TYPE_WISHBONE 0 +#define CHAMELEONV2_MAGIC 0xabce + +typedef struct { + PCIDevice dev; + MCBus bus; + MemoryRegion ctbl; + uint16_t status; + uint8_t int_set; + ChameleonFPGAHeader *header; + + uint8_t minor; + uint8_t rev; + uint8_t model; +} MPCIState; + +#define TYPE_MCB_PCI "mcb-pci" + +#define MPCI(obj) \ + OBJECT_CHECK(MPCIState, (obj), TYPE_MCB_PCI) + +#define CHAMELEON_TABLE_SIZE 0x200 +#define N_MODULES 32 + +#define PCI_VENDOR_ID_MEN 0x1a88 +#define PCI_DEVICE_ID_MEN_MCBPCI 0x4d45 + +static uint32_t read_header(MPCIState *s, hwaddr addr) +{ + uint32_t ret =3D 0; + ChameleonFPGAHeader *header =3D s->header; + + switch (addr / 4) { + case 0: + ret |=3D header->revision; + ret |=3D header->model << 8; + ret |=3D header->minor << 16; + ret |=3D header->bus_type << 24; + break; + case 1: + ret |=3D header->magic; + ret |=3D header->reserved << 16; + break; + case 2: + memcpy(&ret, header->filename, sizeof(uint32_t)); + break; + case 3: + memcpy(&ret, header->filename + sizeof(uint32_t), + sizeof(uint32_t)); + break; + case 4: + memcpy(&ret, header->filename + 2 * sizeof(uint32_t), + sizeof(uint32_t)); + } + + return ret; +} + +static uint32_t read_gdd(MCBDevice *mdev, int reg) +{ + ChameleonDeviceDescriptor *gdd; + uint32_t ret =3D 0; + + gdd =3D mdev->gdd; + + switch (reg) { + case 0: + ret =3D gdd->reg1; + break; + case 1: + ret =3D gdd->reg2; + break; + case 2: + ret =3D gdd->offset; + break; + case 3: + ret =3D gdd->size; + break; + } + + return ret; +} + +static uint64_t mpci_chamtbl_read(void *opaque, hwaddr addr, unsigned size) +{ + MPCIState *s =3D opaque; + MCBus *bus =3D &s->bus; + MCBDevice *mdev; + uint32_t ret =3D 0; + + DPRINTF("Read from address 0x%lx size %d\n", addr, size); + + if (addr < sizeof(ChameleonFPGAHeader)) { + return le32_to_cpu(read_header(s, addr)); + } else if (addr >=3D sizeof(ChameleonFPGAHeader) && + addr < CHAMELEON_TABLE_SIZE) { + /* Handle read on chameleon table */ + BusChild *kid; + DeviceState *qdev; + int slot; + int offset; + int i; + + offset =3D addr - sizeof(ChameleonFPGAHeader); + slot =3D offset / sizeof(ChameleonDeviceDescriptor); + + kid =3D QTAILQ_FIRST(&BUS(bus)->children); + for (i =3D 0; i < slot; i++) { + kid =3D QTAILQ_NEXT(kid, sibling); + if (!kid) { /* Last element */ + DPRINTF("Last element: 0x%08x\n", ~0U); + return ~0U; + } + } + qdev =3D kid->child; + mdev =3D MCB_DEVICE(qdev); + offset -=3D slot * 16; + + ret =3D read_gdd(mdev, offset / 4); + return le32_to_cpu(ret); + } + + return ret; +} + +static void mpci_chamtbl_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + + if (addr < CHAMELEON_TABLE_SIZE) + DPRINTF("Invalid write to 0x%x: 0x%x\n", (unsigned) addr, + (unsigned) val); + + return; +} + +static const MemoryRegionOps mpci_chamtbl_ops =3D { + .read =3D mpci_chamtbl_read, + .write =3D mpci_chamtbl_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + }, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + }, +}; + +static void mcb_pci_set_irq(void *opaque, int intno, int level) +{ + MCBDevice *mdev =3D opaque; + MCBus *bus =3D MCB_BUS(qdev_get_parent_bus(DEVICE(mdev))); + PCIDevice *pcidev =3D PCI_DEVICE(BUS(bus)->parent); + MPCIState *dev =3D MPCI(pcidev); + + if (level) { + pci_set_irq(&dev->dev, !dev->int_set); + pci_set_irq(&dev->dev, dev->int_set); + } else { + uint16_t level_status =3D dev->status; + + if (level_status && !dev->int_set) { + pci_irq_assert(&dev->dev); + dev->int_set =3D 1; + } else if (!level_status && dev->int_set) { + pci_irq_deassert(&dev->dev); + dev->int_set =3D 0; + } + } +} + +static void mcb_pci_write_config(PCIDevice *pci_dev, uint32_t address, + uint32_t val, int len) +{ + pci_default_write_config(pci_dev, address, val, len); +} + +static void mcb_pci_realize(PCIDevice *pci_dev, Error **errp) +{ + MPCIState *s =3D MPCI(pci_dev); + uint8_t *pci_conf =3D s->dev.config; + ChameleonFPGAHeader *header; + MCBus *bus =3D &s->bus; + + header =3D g_new0(ChameleonFPGAHeader, 1); + + s->header =3D header; + + header->revision =3D s->rev; + header->model =3D (char) s->model; + header->minor =3D s->minor; + header->bus_type =3D CHAMELEON_BUS_TYPE_WISHBONE; + header->magic =3D CHAMELEONV2_MAGIC; + memcpy(&header->filename, "QEMU MCB PCI", 12); + + pci_dev->config_write =3D mcb_pci_write_config; + pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 0x01); /* Interrupt pin A */ + pci_conf[PCI_COMMAND] =3D PCI_COMMAND_MEMORY; + + mcb_bus_new_inplace(&s->bus, sizeof(s->bus), DEVICE(pci_dev), NULL, + N_MODULES, mcb_pci_set_irq); + + memory_region_init(&bus->mmio_region, OBJECT(s), "mcb-pci.mmio", + 2048 * 1024); + memory_region_init_io(&s->ctbl, OBJECT(s), &mpci_chamtbl_ops, + s, "mpci_chamtbl_ops", CHAMELEON_TABLE_SIZE); + memory_region_add_subregion(&bus->mmio_region, 0, &s->ctbl); + pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, + &bus->mmio_region); + +} + +static void mcb_pci_unrealize(PCIDevice *pci_dev) +{ + MPCIState *s =3D MPCI(pci_dev); + + g_free(s->header); + s->header =3D NULL; +} + +static const VMStateDescription vmstate_mcb_pci =3D { + .name =3D "mcb-pci", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_PCI_DEVICE(dev, MPCIState), + VMSTATE_END_OF_LIST() + } +}; + +static Property mcb_pci_props[] =3D { + DEFINE_PROP_UINT8("revision", MPCIState, rev, 1), + DEFINE_PROP_UINT8("minor", MPCIState, minor, 0), + DEFINE_PROP_UINT8("model", MPCIState, model, 0x41), + DEFINE_PROP_END_OF_LIST(), +}; + +static void mcb_pci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->realize =3D mcb_pci_realize; + k->exit =3D mcb_pci_unrealize; + k->vendor_id =3D PCI_VENDOR_ID_MEN; + k->device_id =3D PCI_DEVICE_ID_MEN_MCBPCI; + k->class_id =3D PCI_CLASS_BRIDGE_OTHER; + + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + dc->desc =3D "MEN Chameleon Bus over PCI"; + dc->vmsd =3D &vmstate_mcb_pci; + dc->props =3D mcb_pci_props; +} + +static const TypeInfo mcb_pci_info =3D { + .name =3D TYPE_MCB_PCI, + .parent =3D TYPE_PCI_DEVICE, + .instance_size =3D sizeof(MPCIState), + .class_init =3D mcb_pci_class_init, + .interfaces =3D (InterfaceInfo[]) { + { INTERFACE_PCIE_DEVICE }, + { } + }, +}; + +static void mcb_pci_register_types(void) +{ + type_register(&mcb_pci_info); +} +type_init(mcb_pci_register_types); --=20 2.16.4