From nobody Wed Nov 5 07:16:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1536585679121101.6702927567062; Mon, 10 Sep 2018 06:21:19 -0700 (PDT) Received: from localhost ([::1]:51674 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fzM7w-0004Si-Tr for importer@patchew.org; Mon, 10 Sep 2018 09:21:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43287) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fzM4C-0008Tr-RN for qemu-devel@nongnu.org; Mon, 10 Sep 2018 09:17:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fzLrU-00033Z-ER for qemu-devel@nongnu.org; Mon, 10 Sep 2018 09:04:18 -0400 Received: from mx2.suse.de ([195.135.220.15]:40212 helo=mx1.suse.de) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fzLrU-00030K-2a for qemu-devel@nongnu.org; Mon, 10 Sep 2018 09:04:16 -0400 Received: from relay1.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id E9970AE0C; Mon, 10 Sep 2018 13:04:12 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Johannes Thumshirn To: qemu-devel@nongnu.org Date: Mon, 10 Sep 2018 15:04:04 +0200 Message-Id: <20180910130407.24981-2-jthumshirn@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20180910130407.24981-1-jthumshirn@suse.de> References: <20180910130407.24981-1-jthumshirn@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x (no timestamps) [generic] X-Received-From: 195.135.220.15 Subject: [Qemu-devel] [RESEND PATCH v2 1/4] Add MEN Chameleon Bus emulation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Johannes Thumshirn Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The MEN Chameleon Bus (MCB) is an on-chip bus system exposing IP Cores of an FPGA to a outside bus system like PCIe. Signed-off-by: Johannes Thumshirn --- default-configs/pci.mak | 1 + hw/Makefile.objs | 1 + hw/mcb/Makefile.objs | 1 + hw/mcb/mcb.c | 180 ++++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/mcb/mcb.h | 104 ++++++++++++++++++++++++++++ 5 files changed, 287 insertions(+) create mode 100644 hw/mcb/Makefile.objs create mode 100644 hw/mcb/mcb.c create mode 100644 include/hw/mcb/mcb.h diff --git a/default-configs/pci.mak b/default-configs/pci.mak index de53d20ac62c..341498615d6e 100644 --- a/default-configs/pci.mak +++ b/default-configs/pci.mak @@ -46,3 +46,4 @@ CONFIG_VGA=3Dy CONFIG_VGA_PCI=3Dy CONFIG_IVSHMEM_DEVICE=3D$(CONFIG_IVSHMEM) CONFIG_ROCKER=3Dy +CONFIG_MCB=3Dy diff --git a/hw/Makefile.objs b/hw/Makefile.objs index a19c1417ed3e..96ab195a24b9 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -17,6 +17,7 @@ devices-dirs-$(CONFIG_IPACK) +=3D ipack/ devices-dirs-$(CONFIG_IPMI) +=3D ipmi/ devices-dirs-$(CONFIG_SOFTMMU) +=3D isa/ devices-dirs-$(CONFIG_SOFTMMU) +=3D misc/ +devices-dirs-$(CONFIG_MCB) +=3D mcb/ devices-dirs-$(CONFIG_SOFTMMU) +=3D net/ devices-dirs-$(CONFIG_SOFTMMU) +=3D rdma/ devices-dirs-$(CONFIG_SOFTMMU) +=3D nvram/ diff --git a/hw/mcb/Makefile.objs b/hw/mcb/Makefile.objs new file mode 100644 index 000000000000..32427c987c44 --- /dev/null +++ b/hw/mcb/Makefile.objs @@ -0,0 +1 @@ +common-obj-$(CONFIG_MCB) +=3D mcb.o diff --git a/hw/mcb/mcb.c b/hw/mcb/mcb.c new file mode 100644 index 000000000000..a9ec3d13dc86 --- /dev/null +++ b/hw/mcb/mcb.c @@ -0,0 +1,180 @@ +/* + * QEMU MEN Chameleon Bus emulation + * + * Copyright (C) 2016 - 2018 Johannes Thumshirn + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/mcb/mcb.h" + +ChameleonDeviceDescriptor *mcb_new_chameleon_descriptor(MCBus *bus, uint8_= t id, + uint8_t rev, + uint8_t var, + uint32_t size) +{ + BusChild *kid; + ChameleonDeviceDescriptor *gdd; + uint32_t reg1 =3D 0; + uint32_t offset =3D 0x200; + uint32_t end =3D 0; + + gdd =3D g_new0(ChameleonDeviceDescriptor, 1); + if (!gdd) { + return NULL; + } + + reg1 |=3D GDD_DEV(id); + reg1 |=3D GDD_DTY(CHAMELEON_DTYPE_GENERAL); + reg1 |=3D GDD_REV(rev); + reg1 |=3D GDD_VAR(var); + gdd->reg1 =3D cpu_to_le32(reg1); + + QTAILQ_FOREACH(kid, &BUS(bus)->children, sibling) { + DeviceState *qdev =3D kid->child; + MCBDevice *mdev =3D MCB_DEVICE(qdev); + + if (mdev->gdd) { + offset =3D mdev->gdd->offset; + end =3D offset + mdev->gdd->size; + } + } + + gdd->offset =3D offset + end; + gdd->size =3D size; + + return gdd; +} + +static void mcb_irq_handler(void *opaque, int irq_num, int level) +{ + MCBDevice *dev =3D opaque; + MCBus *bus =3D MCB_BUS(qdev_get_parent_bus(DEVICE(dev))); + + if (bus->set_irq) { + bus->set_irq(dev, irq_num, level); + } +} + +qemu_irq mcb_allocate_irq(MCBDevice *dev) +{ + int irq =3D 0; + return qemu_allocate_irq(mcb_irq_handler, dev, irq); +} + +MCBDevice *mcb_device_find(MCBus *bus, hwaddr addr) +{ + BusChild *kid; + uint32_t start; + uint32_t end; + + QTAILQ_FOREACH(kid, &BUS(bus)->children, sibling) { + DeviceState *qdev =3D kid->child; + MCBDevice *mdev =3D MCB_DEVICE(qdev); + + start =3D mdev->gdd->offset; + end =3D start + mdev->gdd->size; + + if (addr >=3D start && addr <=3D end) { + return mdev; + } + } + return NULL; +} + +void mcb_bus_new_inplace(MCBus *bus, size_t bus_size, + DeviceState *parent, + const char *name, uint8_t slots, + qemu_irq_handler handler) +{ + qbus_create_inplace(bus, bus_size, TYPE_MCB_BUS, parent, name); + bus->n_slots =3D slots; + bus->set_irq =3D handler; +} + +static void mcb_device_realize(DeviceState *dev, Error **errp) +{ + MCBDevice *mdev =3D MCB_DEVICE(dev); + MCBus *bus =3D MCB_BUS(qdev_get_parent_bus(dev)); + MCBDeviceClass *k =3D MCB_DEVICE_GET_CLASS(dev); + + if (mdev->slot < 0) { + mdev->slot =3D bus->free_slot; + } + + if (mdev->slot >=3D bus->n_slots) { + error_setg(errp, "Only %" PRIu8 " slots available.", bus->n_slots); + return; + } + bus->free_slot =3D mdev->slot + 1; + + mdev->irq =3D qemu_allocate_irqs(bus->set_irq, mdev, 1); + + k->realize(dev, errp); +} + +static void mcb_device_unrealize(DeviceState *dev, Error **errp) +{ + MCBDevice *mdev =3D MCB_DEVICE(dev); + MCBDeviceClass *k =3D MCB_DEVICE_GET_CLASS(dev); + Error *err =3D NULL; + + if (k->unrealize) { + k->unrealize(dev, &err); + error_propagate(errp, err); + return; + } + + qemu_free_irqs(mdev->irq, 1); +} + +static Property mcb_device_props[] =3D { + DEFINE_PROP_INT32("slot", MCBDevice, slot, -1), + DEFINE_PROP_END_OF_LIST() +}; + +static void mcb_device_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *k =3D DEVICE_CLASS(klass); + + set_bit(DEVICE_CATEGORY_INPUT, k->categories); + k->bus_type =3D TYPE_MCB_BUS; + k->realize =3D mcb_device_realize; + k->unrealize =3D mcb_device_unrealize; + k->props =3D mcb_device_props; +} + +const VMStateDescription vmstate_mcb_device =3D { + .name =3D "mcb_device", + .version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_INT32(slot, MCBDevice), + VMSTATE_END_OF_LIST() + } +}; + +static const TypeInfo mcb_device_info =3D { + .name =3D TYPE_MCB_DEVICE, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(MCBDevice), + .class_size =3D sizeof(MCBDeviceClass), + .class_init =3D mcb_device_class_init, + .abstract =3D true, +}; + +static const TypeInfo mcb_bus_info =3D { + .name =3D TYPE_MCB_BUS, + .parent =3D TYPE_BUS, + .instance_size =3D sizeof(MCBus), +}; + +static void mcb_register_types(void) +{ + type_register_static(&mcb_device_info); + type_register_static(&mcb_bus_info); +} + +type_init(mcb_register_types); diff --git a/include/hw/mcb/mcb.h b/include/hw/mcb/mcb.h new file mode 100644 index 000000000000..e546d2319182 --- /dev/null +++ b/include/hw/mcb/mcb.h @@ -0,0 +1,104 @@ +/* + * QEMU MEN Chameleon Bus emulation + * + * Copyright (C) 2016 - 2018 Johannes Thumshirn + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#ifndef QEMU_MCB_H +#define QEMU_MCB_H + +#include "hw/qdev.h" + +#define CHAMELEON_DTYPE_GENERAL 0x0 +#define CHAMELEON_DTYPE_END 0xf + +typedef struct { + uint32_t reg1; + uint32_t reg2; + uint32_t offset; + uint32_t size; +} ChameleonDeviceDescriptor; + +#define GDD_DEV(x) (((x) & 0x3ff) << 18) +#define GDD_DTY(x) (((x) & 0xf) << 28) +#define GDD_REV(x) (((x) & 0x3f) << 5) +#define GDD_VAR(x) (((x) & 0x3f) << 11) + +/* GDD Register 1 fields */ +#define GDD_IRQ(x) ((x) & 0x1f) + +/* GDD Register 2 fields */ +#define GDD_BAR(x) ((x) & 0x7) +#define GDD_INS(x) (((x) >> 3) & 0x3f) +#define GDD_GRP(x) (((x) >> 9) & 0x3f) + +typedef struct MCBus MCBus; + +#define TYPE_MCB_BUS "MEN Chameleon Bus" +#define MCB_BUS(obj) OBJECT_CHECK(MCBus, (obj), TYPE_MCB_BUS) + +struct MCBus { + /*< private >*/ + BusState parent_obj; + + uint8_t n_slots; + uint8_t free_slot; + qemu_irq_handler set_irq; + MemoryRegion mmio_region; +}; + +typedef struct MCBDevice MCBDevice; +typedef struct MCBDeviceClass MCBDeviceClass; + +#define TYPE_MCB_DEVICE "mcb-device" +#define MCB_DEVICE(obj) \ + OBJECT_CHECK(MCBDevice, (obj), TYPE_MCB_DEVICE) +#define MCB_DEVICE_CLASS(klass) \ + OBJECT_CLASS_CHECK(MCBDeviceClass, (klass), TYPE_MCB_DEVICE) +#define MCB_DEVICE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(MCBDeviceClass, (obj), TYPE_MCB_DEVICE) + +struct MCBDeviceClass { + /*< private >*/ + DeviceClass parent_class; + /*< public >*/ + + + DeviceRealize realize; + DeviceUnrealize unrealize; +}; + +struct MCBDevice { + /*< private >*/ + DeviceState parent_obj; + /*< public >*/ + + qemu_irq *irq; + ChameleonDeviceDescriptor *gdd; + int slot; + + uint8_t rev; + uint8_t var; +}; + +extern const VMStateDescription vmstate_mcb_device; + +ChameleonDeviceDescriptor *mcb_new_chameleon_descriptor(MCBus *bus, uint8_= t id, + uint8_t rev, + uint8_t var, + uint32_t size); + +#define VMSTATE_MCB_DEVICE(_field, _state) \ + VMSTATE_STRUCT(_field, _state, 1, vmstate_mcb_device, MCBDevice) + +MCBDevice *mcb_device_find(MCBus *bus, hwaddr addr); +void mcb_bus_new_inplace(MCBus *bus, size_t bus_size, + DeviceState *parent, + const char *name, uint8_t slots, + qemu_irq_handler handler); + +qemu_irq mcb_allocate_irq(MCBDevice *dev); +#endif --=20 2.16.4 From nobody Wed Nov 5 07:16:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1536585692580794.6819887466897; Mon, 10 Sep 2018 06:21:32 -0700 (PDT) Received: from localhost ([::1]:51675 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fzM86-0004ah-KC for importer@patchew.org; Mon, 10 Sep 2018 09:21:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42680) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fzM49-0008Bz-NQ for qemu-devel@nongnu.org; Mon, 10 Sep 2018 09:17:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fzLrX-00036P-Au for qemu-devel@nongnu.org; Mon, 10 Sep 2018 09:04:23 -0400 Received: from mx2.suse.de ([195.135.220.15]:40204 helo=mx1.suse.de) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fzLrU-00030C-Iy for qemu-devel@nongnu.org; Mon, 10 Sep 2018 09:04:18 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id EA55AAEB2; Mon, 10 Sep 2018 13:04:12 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Johannes Thumshirn To: qemu-devel@nongnu.org Date: Mon, 10 Sep 2018 15:04:05 +0200 Message-Id: <20180910130407.24981-3-jthumshirn@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20180910130407.24981-1-jthumshirn@suse.de> References: <20180910130407.24981-1-jthumshirn@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x (no timestamps) [generic] X-Received-From: 195.135.220.15 Subject: [Qemu-devel] [RESEND PATCH v2 2/4] Add MEN Chameleon Bus via PCI carrier X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Johannes Thumshirn Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Johannes Thumshirn --- hw/mcb/Makefile.objs | 1 + hw/mcb/mcb-pci.c | 305 +++++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 306 insertions(+) create mode 100644 hw/mcb/mcb-pci.c diff --git a/hw/mcb/Makefile.objs b/hw/mcb/Makefile.objs index 32427c987c44..125f4a84700a 100644 --- a/hw/mcb/Makefile.objs +++ b/hw/mcb/Makefile.objs @@ -1 +1,2 @@ common-obj-$(CONFIG_MCB) +=3D mcb.o +common-obj-$(CONFIG_MCB) +=3D mcb-pci.o diff --git a/hw/mcb/mcb-pci.c b/hw/mcb/mcb-pci.c new file mode 100644 index 000000000000..a1a47980766f --- /dev/null +++ b/hw/mcb/mcb-pci.c @@ -0,0 +1,305 @@ +/* + * QEMU MEN Chameleon Bus emulation + * + * Copyright (C) 2016 - 2018 Johannes Thumshirn + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/mcb/mcb.h" +#include "hw/pci/pci.h" + +/* #define DEBUG_MPCI 1 */ + +#ifdef DEBUG_MPCI +#define DPRINTF(fmt, ...) \ + do { fprintf(stderr, "mcb-pci: " fmt, ## __VA_ARGS__); } while (0) +#else +#define DPRINTF(fmt, ...) do { } while (0) +#endif + +typedef struct { + uint8_t revision; + char model; + uint8_t minor; + uint8_t bus_type; + uint16_t magic; + uint16_t reserved; + /* This one has no '\0' at the end!!! */ + char filename[12]; +} ChameleonFPGAHeader; +#define CHAMELEON_BUS_TYPE_WISHBONE 0 +#define CHAMELEONV2_MAGIC 0xabce + +typedef struct { + PCIDevice dev; + MCBus bus; + MemoryRegion ctbl; + uint16_t status; + uint8_t int_set; + ChameleonFPGAHeader *header; + + uint8_t minor; + uint8_t rev; + uint8_t model; +} MPCIState; + +#define TYPE_MCB_PCI "mcb-pci" + +#define MPCI(obj) \ + OBJECT_CHECK(MPCIState, (obj), TYPE_MCB_PCI) + +#define CHAMELEON_TABLE_SIZE 0x200 +#define N_MODULES 32 + +#define PCI_VENDOR_ID_MEN 0x1a88 +#define PCI_DEVICE_ID_MEN_MCBPCI 0x4d45 + +static uint32_t read_header(MPCIState *s, hwaddr addr) +{ + uint32_t ret =3D 0; + ChameleonFPGAHeader *header =3D s->header; + + switch (addr / 4) { + case 0: + ret |=3D header->revision; + ret |=3D header->model << 8; + ret |=3D header->minor << 16; + ret |=3D header->bus_type << 24; + break; + case 1: + ret |=3D header->magic; + ret |=3D header->reserved << 16; + break; + case 2: + memcpy(&ret, header->filename, sizeof(uint32_t)); + break; + case 3: + memcpy(&ret, header->filename + sizeof(uint32_t), + sizeof(uint32_t)); + break; + case 4: + memcpy(&ret, header->filename + 2 * sizeof(uint32_t), + sizeof(uint32_t)); + } + + return ret; +} + +static uint32_t read_gdd(MCBDevice *mdev, int reg) +{ + ChameleonDeviceDescriptor *gdd; + uint32_t ret =3D 0; + + gdd =3D mdev->gdd; + + switch (reg) { + case 0: + ret =3D gdd->reg1; + break; + case 1: + ret =3D gdd->reg2; + break; + case 2: + ret =3D gdd->offset; + break; + case 3: + ret =3D gdd->size; + break; + } + + return ret; +} + +static uint64_t mpci_chamtbl_read(void *opaque, hwaddr addr, unsigned size) +{ + MPCIState *s =3D opaque; + MCBus *bus =3D &s->bus; + MCBDevice *mdev; + uint32_t ret =3D 0; + + DPRINTF("Read from address 0x%lx size %d\n", addr, size); + + if (addr < sizeof(ChameleonFPGAHeader)) { + return le32_to_cpu(read_header(s, addr)); + } else if (addr >=3D sizeof(ChameleonFPGAHeader) && + addr < CHAMELEON_TABLE_SIZE) { + /* Handle read on chameleon table */ + BusChild *kid; + DeviceState *qdev; + int slot; + int offset; + int i; + + offset =3D addr - sizeof(ChameleonFPGAHeader); + slot =3D offset / sizeof(ChameleonDeviceDescriptor); + + kid =3D QTAILQ_FIRST(&BUS(bus)->children); + for (i =3D 0; i < slot; i++) { + kid =3D QTAILQ_NEXT(kid, sibling); + if (!kid) { /* Last element */ + DPRINTF("Last element: 0x%08x\n", ~0U); + return ~0U; + } + } + qdev =3D kid->child; + mdev =3D MCB_DEVICE(qdev); + offset -=3D slot * 16; + + ret =3D read_gdd(mdev, offset / 4); + return le32_to_cpu(ret); + } + + return ret; +} + +static void mpci_chamtbl_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + + if (addr < CHAMELEON_TABLE_SIZE) + DPRINTF("Invalid write to 0x%x: 0x%x\n", (unsigned) addr, + (unsigned) val); + + return; +} + +static const MemoryRegionOps mpci_chamtbl_ops =3D { + .read =3D mpci_chamtbl_read, + .write =3D mpci_chamtbl_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + }, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + }, +}; + +static void mcb_pci_set_irq(void *opaque, int intno, int level) +{ + MCBDevice *mdev =3D opaque; + MCBus *bus =3D MCB_BUS(qdev_get_parent_bus(DEVICE(mdev))); + PCIDevice *pcidev =3D PCI_DEVICE(BUS(bus)->parent); + MPCIState *dev =3D MPCI(pcidev); + + if (level) { + pci_set_irq(&dev->dev, !dev->int_set); + pci_set_irq(&dev->dev, dev->int_set); + } else { + uint16_t level_status =3D dev->status; + + if (level_status && !dev->int_set) { + pci_irq_assert(&dev->dev); + dev->int_set =3D 1; + } else if (!level_status && dev->int_set) { + pci_irq_deassert(&dev->dev); + dev->int_set =3D 0; + } + } +} + +static void mcb_pci_write_config(PCIDevice *pci_dev, uint32_t address, + uint32_t val, int len) +{ + pci_default_write_config(pci_dev, address, val, len); +} + +static void mcb_pci_realize(PCIDevice *pci_dev, Error **errp) +{ + MPCIState *s =3D MPCI(pci_dev); + uint8_t *pci_conf =3D s->dev.config; + ChameleonFPGAHeader *header; + MCBus *bus =3D &s->bus; + + header =3D g_new0(ChameleonFPGAHeader, 1); + + s->header =3D header; + + header->revision =3D s->rev; + header->model =3D (char) s->model; + header->minor =3D s->minor; + header->bus_type =3D CHAMELEON_BUS_TYPE_WISHBONE; + header->magic =3D CHAMELEONV2_MAGIC; + memcpy(&header->filename, "QEMU MCB PCI", 12); + + pci_dev->config_write =3D mcb_pci_write_config; + pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 0x01); /* Interrupt pin A */ + pci_conf[PCI_COMMAND] =3D PCI_COMMAND_MEMORY; + + mcb_bus_new_inplace(&s->bus, sizeof(s->bus), DEVICE(pci_dev), NULL, + N_MODULES, mcb_pci_set_irq); + + memory_region_init(&bus->mmio_region, OBJECT(s), "mcb-pci.mmio", + 2048 * 1024); + memory_region_init_io(&s->ctbl, OBJECT(s), &mpci_chamtbl_ops, + s, "mpci_chamtbl_ops", CHAMELEON_TABLE_SIZE); + memory_region_add_subregion(&bus->mmio_region, 0, &s->ctbl); + pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, + &bus->mmio_region); + +} + +static void mcb_pci_unrealize(PCIDevice *pci_dev) +{ + MPCIState *s =3D MPCI(pci_dev); + + g_free(s->header); + s->header =3D NULL; +} + +static const VMStateDescription vmstate_mcb_pci =3D { + .name =3D "mcb-pci", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_PCI_DEVICE(dev, MPCIState), + VMSTATE_END_OF_LIST() + } +}; + +static Property mcb_pci_props[] =3D { + DEFINE_PROP_UINT8("revision", MPCIState, rev, 1), + DEFINE_PROP_UINT8("minor", MPCIState, minor, 0), + DEFINE_PROP_UINT8("model", MPCIState, model, 0x41), + DEFINE_PROP_END_OF_LIST(), +}; + +static void mcb_pci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->realize =3D mcb_pci_realize; + k->exit =3D mcb_pci_unrealize; + k->vendor_id =3D PCI_VENDOR_ID_MEN; + k->device_id =3D PCI_DEVICE_ID_MEN_MCBPCI; + k->class_id =3D PCI_CLASS_BRIDGE_OTHER; + + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + dc->desc =3D "MEN Chameleon Bus over PCI"; + dc->vmsd =3D &vmstate_mcb_pci; + dc->props =3D mcb_pci_props; +} + +static const TypeInfo mcb_pci_info =3D { + .name =3D TYPE_MCB_PCI, + .parent =3D TYPE_PCI_DEVICE, + .instance_size =3D sizeof(MPCIState), + .class_init =3D mcb_pci_class_init, + .interfaces =3D (InterfaceInfo[]) { + { INTERFACE_PCIE_DEVICE }, + { } + }, +}; + +static void mcb_pci_register_types(void) +{ + type_register(&mcb_pci_info); +} +type_init(mcb_pci_register_types); --=20 2.16.4 From nobody Wed Nov 5 07:16:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1536585849181692.238014756415; Mon, 10 Sep 2018 06:24:09 -0700 (PDT) Received: from localhost ([::1]:51696 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fzMAi-00080F-8c for importer@patchew.org; Mon, 10 Sep 2018 09:24:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43290) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fzM4C-0008Ts-In for qemu-devel@nongnu.org; Mon, 10 Sep 2018 09:17:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fzLrU-00033Q-CA for qemu-devel@nongnu.org; Mon, 10 Sep 2018 09:04:22 -0400 Received: from mx2.suse.de ([195.135.220.15]:40206 helo=mx1.suse.de) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fzLrU-00030G-0J for qemu-devel@nongnu.org; Mon, 10 Sep 2018 09:04:16 -0400 Received: from relay1.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id E981AAD83; Mon, 10 Sep 2018 13:04:12 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Johannes Thumshirn To: qemu-devel@nongnu.org Date: Mon, 10 Sep 2018 15:04:06 +0200 Message-Id: <20180910130407.24981-4-jthumshirn@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20180910130407.24981-1-jthumshirn@suse.de> References: <20180910130407.24981-1-jthumshirn@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x (no timestamps) [generic] X-Received-From: 195.135.220.15 Subject: [Qemu-devel] [RESEND PATCH v2 3/4] serial-mcb: Add serial via MEN chameleon bus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Johannes Thumshirn Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add MEN z125 UART over MEN Chameleon Bus emulation. Signed-off-by: Johannes Thumshirn --- hw/char/Makefile.objs | 1 + hw/char/serial-mcb.c | 100 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 101 insertions(+) create mode 100644 hw/char/serial-mcb.c diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs index b57053129107..063f1720974d 100644 --- a/hw/char/Makefile.objs +++ b/hw/char/Makefile.objs @@ -6,6 +6,7 @@ common-obj-$(CONFIG_PL011) +=3D pl011.o common-obj-$(CONFIG_SERIAL) +=3D serial.o common-obj-$(CONFIG_SERIAL_ISA) +=3D serial-isa.o common-obj-$(CONFIG_SERIAL_PCI) +=3D serial-pci.o +common-obj-$(CONFIG_MCB) +=3D serial-mcb.o common-obj-$(CONFIG_VIRTIO_SERIAL) +=3D virtio-console.o common-obj-$(CONFIG_XILINX) +=3D xilinx_uartlite.o common-obj-$(CONFIG_XEN) +=3D xen_console.o diff --git a/hw/char/serial-mcb.c b/hw/char/serial-mcb.c new file mode 100644 index 000000000000..5e1ef27815c6 --- /dev/null +++ b/hw/char/serial-mcb.c @@ -0,0 +1,100 @@ +/* + * QEMU MEN 16z125 UART over MCB emulation + * + * Copyright (C) 2016 - 2018 Johannes Thumshirn + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/char/serial.h" +#include "hw/mcb/mcb.h" + +typedef struct { + /*< private >*/ + MCBDevice dev; + /*< public >*/ + + SerialState state; +} MCBSerialState; + +static void serial_mcb_realize(DeviceState *dev, Error **errp) +{ + MCBDevice *mdev =3D MCB_DEVICE(dev); + MCBSerialState *mss =3D DO_UPCAST(MCBSerialState, dev, mdev); + MCBus *bus =3D MCB_BUS(qdev_get_parent_bus(DEVICE(dev))); + SerialState *s =3D &mss->state; + Error *err =3D 0; + + mdev->gdd =3D mcb_new_chameleon_descriptor(bus, 125, mdev->rev, + mdev->var, 0x10); + if (!mdev->gdd) { + return; + } + + s->baudbase =3D 115200; + serial_realize_core(s, &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + + s->irq =3D mcb_allocate_irq(&mss->dev); + memory_region_init_io(&s->io, OBJECT(mss), &serial_io_ops, s, "serial"= , 8); + memory_region_add_subregion(&bus->mmio_region, mdev->gdd->offset, &s->= io); +} + +static void serial_mcb_unrealize(DeviceState *dev, Error **errp) +{ + MCBDevice *mdev =3D MCB_DEVICE(dev); + + g_free(&mdev->gdd); +} + +static const VMStateDescription vmstate_mcb_serial =3D { + .name =3D "mcb-serial", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_MCB_DEVICE(dev, MCBSerialState), + VMSTATE_STRUCT(state, MCBSerialState, 0, vmstate_serial, SerialSta= te), + VMSTATE_END_OF_LIST() + } +}; + +static Property serial_mcb_properties[] =3D { + DEFINE_PROP_CHR("chardev", MCBSerialState, state.chr), + DEFINE_PROP_UINT8("rev", MCBSerialState, dev.rev, 0), + DEFINE_PROP_UINT8("var", MCBSerialState, dev.var, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void serial_mcb_class_initfn(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + MCBDeviceClass *mc =3D MCB_DEVICE_CLASS(klass); + + mc->realize =3D serial_mcb_realize; + mc->unrealize =3D serial_mcb_unrealize; + + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); + dc->desc =3D "MEN 16z125 UART over MCB"; + dc->vmsd =3D &vmstate_mcb_serial; + dc->props =3D serial_mcb_properties; +} + +static const TypeInfo serial_mcb_info =3D { + .name =3D "mcb-serial", + .parent =3D TYPE_MCB_DEVICE, + .instance_size =3D sizeof(MCBSerialState), + .class_init =3D serial_mcb_class_initfn, +}; + +static void serial_mcb_register_types(void) +{ + type_register_static(&serial_mcb_info); +} + +type_init(serial_mcb_register_types); --=20 2.16.4 From nobody Wed Nov 5 07:16:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153658554999394.02279257040493; Mon, 10 Sep 2018 06:19:09 -0700 (PDT) Received: from localhost ([::1]:51661 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fzM5s-0002ox-Bi for importer@patchew.org; Mon, 10 Sep 2018 09:19:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43565) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fzM49-00005q-OX for qemu-devel@nongnu.org; Mon, 10 Sep 2018 09:17:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fzLrU-00033e-Ew for qemu-devel@nongnu.org; Mon, 10 Sep 2018 09:04:22 -0400 Received: from mx2.suse.de ([195.135.220.15]:40216 helo=mx1.suse.de) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fzLrU-00030Q-38 for qemu-devel@nongnu.org; Mon, 10 Sep 2018 09:04:16 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id E9B74AE26; Mon, 10 Sep 2018 13:04:12 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Johannes Thumshirn To: qemu-devel@nongnu.org Date: Mon, 10 Sep 2018 15:04:07 +0200 Message-Id: <20180910130407.24981-5-jthumshirn@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20180910130407.24981-1-jthumshirn@suse.de> References: <20180910130407.24981-1-jthumshirn@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x (no timestamps) [generic] X-Received-From: 195.135.220.15 Subject: [Qemu-devel] [RESEND PATCH v2 4/4] wdt_z069: Add support for MEN 16z069 Watchdog X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Johannes Thumshirn Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add 16z069 Watchdog over MEN Chameleon BUS emulation. Signed-off-by: Johannes Thumshirn --- hw/watchdog/Makefile.objs | 1 + hw/watchdog/wdt_z069.c | 215 ++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 216 insertions(+) create mode 100644 hw/watchdog/wdt_z069.c diff --git a/hw/watchdog/Makefile.objs b/hw/watchdog/Makefile.objs index 9589bed63a3d..ada010f1eb69 100644 --- a/hw/watchdog/Makefile.objs +++ b/hw/watchdog/Makefile.objs @@ -3,3 +3,4 @@ common-obj-$(CONFIG_WDT_IB6300ESB) +=3D wdt_i6300esb.o common-obj-$(CONFIG_WDT_IB700) +=3D wdt_ib700.o common-obj-$(CONFIG_WDT_DIAG288) +=3D wdt_diag288.o common-obj-$(CONFIG_ASPEED_SOC) +=3D wdt_aspeed.o +common-obj-$(CONFIG_MCB) +=3D wdt_z069.o diff --git a/hw/watchdog/wdt_z069.c b/hw/watchdog/wdt_z069.c new file mode 100644 index 000000000000..9cd900bfdc17 --- /dev/null +++ b/hw/watchdog/wdt_z069.c @@ -0,0 +1,215 @@ +/* + * QEMU MEN 16z069 Watchdog over MCB emulation + * + * Copyright (C) 2018 Johannes Thumshirn + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ +#include "qemu/osdep.h" +#include "qemu/timer.h" +#include "sysemu/watchdog.h" +#include "hw/mcb/mcb.h" + +/* #define Z069_DEBUG 1 */ + +#ifdef Z069_DEBUG +#define z069_debug(fmt, ...) \ + fprintf(stderr, "wdt_z069: %s: "fmt, __func__, ##__VA_ARGS__) +#else +#define z069_debug(fmt, ...) +#endif + +#define MEN_Z069_WTR 0x10 +#define MEN_Z069_WTR_WDEN BIT(15) +#define MEN_Z069_WTR_WDET_MASK 0x7fff +#define MEN_Z069_WVR 0x14 + +#define CLK_500(x) ((x) * 2) /* 500Hz in ms */ + +typedef struct { + /*< private >*/ + MCBDevice dev; + + /*< public >*/ + QEMUTimer *timer; + + bool enabled; + unsigned int timeout; + + MemoryRegion mmio; + + /* Registers */ + uint16_t wtr; + uint16_t wvr; +} MENZ069State; + +static void men_z069_wdt_enable(MENZ069State *s) +{ + z069_debug("next timeout will fire in +%dms\n", s->timeout); + timer_mod(s->timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->timeout= ); +} + +static void men_z069_wdt_disable(MENZ069State *s) +{ + timer_del(s->timer); +} + +static uint64_t men_z069_wdt_read(void *opaque, hwaddr addr, unsigned size) +{ + MENZ069State *s =3D opaque; + uint64_t ret; + + switch (addr) { + case MEN_Z069_WTR: + ret =3D s->wtr; + break; + case MEN_Z069_WVR: + ret =3D s->wvr; + break; + default: + ret =3D 0UL; + break; + } + + z069_debug("returning: 0x%"PRIx64" @ 0x%lx\n", ret, addr); + return ret; +} + +static void men_z069_wdt_write(void *opaque, hwaddr addr, uint64_t v, + unsigned size) +{ + MENZ069State *s =3D opaque; + bool old_ena =3D s->enabled; + uint16_t val =3D v & 0xffff; + uint16_t tout; + + z069_debug("got: 0x%"PRIx64" @ 0x%lx\n", v, addr); + + switch (addr) { + case MEN_Z069_WTR: + s->wtr =3D val; + tout =3D val & MEN_Z069_WTR_WDET_MASK; + s->timeout =3D CLK_500(tout); + s->enabled =3D val & MEN_Z069_WTR_WDEN; + z069_debug("new timeout: %u (0x%x) %u\n", tout, tout, s->timeout); + + if (old_ena && !s->enabled) { + men_z069_wdt_disable(s); + } else if (!old_ena && s->enabled) { + men_z069_wdt_enable(s); + } + + break; + case MEN_Z069_WVR: + /* The watchdog trigger value toggles between 0x5555 and 0xaaaa */ + if (val =3D=3D (s->wvr ^ 0xffff)) { + s->wvr =3D val; + z069_debug("watchdog triggered, next timeout will fire in +%dm= s\n", + s->timeout); + timer_mod(s->timer, + qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->timeout); + } + break; + default: + break; + } + return; +} + +static const MemoryRegionOps men_z069_io_ops =3D { + .read =3D men_z069_wdt_read, + .write =3D men_z069_wdt_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + }, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + }, +}; + +static void men_z069_timer_expired(void *opaque) +{ + MENZ069State *s =3D opaque; + + watchdog_perform_action(); + timer_del(s->timer); +} + +static void men_z069_wdt_realize(DeviceState *dev, Error **errp) +{ + MCBDevice *mdev =3D MCB_DEVICE(dev); + MENZ069State *s =3D DO_UPCAST(MENZ069State, dev, mdev); + MCBus *bus =3D MCB_BUS(qdev_get_parent_bus(DEVICE(dev))); + + mdev->gdd =3D mcb_new_chameleon_descriptor(bus, 69, mdev->rev, + mdev->var, 0x18); + if (!mdev->gdd) { + return; + } + + s->wvr =3D 0x5555; + s->wtr =3D 0x7fff; + s->timeout =3D CLK_500(s->wtr & MEN_Z069_WTR_WDET_MASK); + s->timer =3D timer_new_ms(QEMU_CLOCK_VIRTUAL, + men_z069_timer_expired, s); + + memory_region_init_io(&s->mmio, OBJECT(s), + &men_z069_io_ops, s, "z069.wdt", 0x16); + memory_region_add_subregion(&bus->mmio_region, mdev->gdd->offset, + &s->mmio); +} + +static void men_z069_wdt_unrealize(DeviceState *dev, Error **errp) +{ + MCBDevice *mdev =3D MCB_DEVICE(dev); + + g_free(&mdev->gdd); +} + +static const VMStateDescription vmstate_z069_wdt =3D { + .name =3D "z069-wdt", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_MCB_DEVICE(dev, MENZ069State), + VMSTATE_TIMER_PTR(timer, MENZ069State), + VMSTATE_END_OF_LIST() + } +}; + +static Property men_z069_wdt_properties[] =3D { + DEFINE_PROP_UINT8("rev", MENZ069State, dev.rev, 0), + DEFINE_PROP_UINT8("var", MENZ069State, dev.var, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void men_z069_wdt_class_intifn(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + MCBDeviceClass *mc =3D MCB_DEVICE_CLASS(klass); + + mc->realize =3D men_z069_wdt_realize; + mc->unrealize =3D men_z069_wdt_unrealize; + + dc->desc =3D "MEN 16z069 Watchdog Timer"; + dc->vmsd =3D &vmstate_z069_wdt; + dc->props =3D men_z069_wdt_properties; +} + +static const TypeInfo men_z069_wdt_info =3D { + .name =3D "z069-wdt", + .parent =3D TYPE_MCB_DEVICE, + .instance_size =3D sizeof(MENZ069State), + .class_init =3D men_z069_wdt_class_intifn, +}; + +static void men_z069_wdt_register_types(void) +{ + type_register_static(&men_z069_wdt_info); +} + +type_init(men_z069_wdt_register_types); --=20 2.16.4