From nobody Wed Nov 5 18:34:59 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1536357381506473.37739155781037; Fri, 7 Sep 2018 14:56:21 -0700 (PDT) Received: from localhost ([::1]:40435 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fyOjk-0004iY-By for importer@patchew.org; Fri, 07 Sep 2018 17:56:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60795) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fyOez-00005C-RZ for qemu-devel@nongnu.org; Fri, 07 Sep 2018 17:51:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fyOey-0005qC-OH for qemu-devel@nongnu.org; Fri, 07 Sep 2018 17:51:25 -0400 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:51492 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fyOey-0005pk-Fo for qemu-devel@nongnu.org; Fri, 07 Sep 2018 17:51:24 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 0EE8E40216E7; Fri, 7 Sep 2018 21:51:24 +0000 (UTC) Received: from redhat.com (ovpn-124-199.rdu2.redhat.com [10.10.124.199]) by smtp.corp.redhat.com (Postfix) with SMTP id AE2F62027EA4; Fri, 7 Sep 2018 21:51:23 +0000 (UTC) Date: Fri, 7 Sep 2018 17:51:23 -0400 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Message-ID: <20180907215109.146867-4-mst@redhat.com> References: <20180907215109.146867-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20180907215109.146867-1-mst@redhat.com> X-Mutt-Fcc: =sent X-Scanned-By: MIMEDefang 2.78 on 10.11.54.4 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Fri, 07 Sep 2018 21:51:24 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Fri, 07 Sep 2018 21:51:24 +0000 (UTC) for IP:'10.11.54.4' DOMAIN:'int-mx04.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'mst@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [PULL 3/7] hw/pci: factor PCI reserve resources to a separate structure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jing Liu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jing Liu Factor "bus_reserve", "io_reserve", "mem_reserve", "pref32_reserve" and "pref64_reserve" fields of the "GenPCIERootPort" structure out to "PCIResReserve" structure, so that other PCI bridges can reuse it to add resource reserve capability. Signed-off-by: Jing Liu Reviewed-by: Marcel Apfelbaum Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/pci/pci_bridge.h | 18 ++++++++++---- hw/pci-bridge/gen_pcie_root_port.c | 33 +++++++++++++------------- hw/pci/pci_bridge.c | 38 +++++++++++++----------------- 3 files changed, 47 insertions(+), 42 deletions(-) diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index 0347da52d2..cdff7edfd1 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -133,11 +133,19 @@ typedef struct PCIBridgeQemuCap { =20 #define REDHAT_PCI_CAP_RESOURCE_RESERVE 1 =20 +/* + * PCI BUS/IO/MEM/PREFMEM additional resources recorded as a + * capability in PCI configuration space to reserve on firmware init. + */ +typedef struct PCIResReserve { + uint32_t bus; + uint64_t io; + uint64_t mem_non_pref; + uint64_t mem_pref_32; + uint64_t mem_pref_64; +} PCIResReserve; + int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, - uint32_t bus_reserve, uint64_t io_reserve, - uint64_t mem_non_pref_reserve, - uint64_t mem_pref_32_reserve, - uint64_t mem_pref_64_reserve, - Error **errp); + PCIResReserve res_reserve, Error **errp); =20 #endif /* QEMU_PCI_BRIDGE_H */ diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_ro= ot_port.c index d117e20325..299de429ec 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -29,12 +29,8 @@ typedef struct GenPCIERootPort { =20 bool migrate_msix; =20 - /* additional resources to reserve on firmware init */ - uint32_t bus_reserve; - uint64_t io_reserve; - uint64_t mem_reserve; - uint64_t pref32_reserve; - uint64_t pref64_reserve; + /* additional resources to reserve */ + PCIResReserve res_reserve; } GenPCIERootPort; =20 static uint8_t gen_rp_aer_vector(const PCIDevice *d) @@ -82,16 +78,15 @@ static void gen_rp_realize(DeviceState *dev, Error **er= rp) return; } =20 - int rc =3D pci_bridge_qemu_reserve_cap_init(d, 0, grp->bus_reserve, - grp->io_reserve, grp->mem_reserve, grp->pref32_reserve, - grp->pref64_reserve, errp); + int rc =3D pci_bridge_qemu_reserve_cap_init(d, 0, + grp->res_reserve, errp); =20 if (rc < 0) { rpc->parent_class.exit(d); return; } =20 - if (!grp->io_reserve) { + if (!grp->res_reserve.io) { pci_word_test_and_clear_mask(d->wmask + PCI_COMMAND, PCI_COMMAND_IO); d->wmask[PCI_IO_BASE] =3D 0; @@ -117,12 +112,18 @@ static const VMStateDescription vmstate_rp_dev =3D { }; =20 static Property gen_rp_props[] =3D { - DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, migrate_msix, true= ), - DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort, bus_reserve, -1), - DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort, io_reserve, -1), - DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort, mem_reserve, -1), - DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort, pref32_reserve, -1= ), - DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, pref64_reserve, -1= ), + DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, + migrate_msix, true), + DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort, + res_reserve.bus, -1), + DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort, + res_reserve.io, -1), + DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort, + res_reserve.mem_non_pref, -1), + DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort, + res_reserve.mem_pref_32, -1), + DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, + res_reserve.mem_pref_64, -1), DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index 40a39f57cb..08b7e44e2e 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -411,38 +411,34 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bu= s_name, =20 =20 int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, - uint32_t bus_reserve, uint64_t io_res= erve, - uint64_t mem_non_pref_reserve, - uint64_t mem_pref_32_reserve, - uint64_t mem_pref_64_reserve, - Error **errp) + PCIResReserve res_reserve, Error **er= rp) { - if (mem_pref_32_reserve !=3D (uint64_t)-1 && - mem_pref_64_reserve !=3D (uint64_t)-1) { + if (res_reserve.mem_pref_32 !=3D (uint64_t)-1 && + res_reserve.mem_pref_64 !=3D (uint64_t)-1) { error_setg(errp, "PCI resource reserve cap: PREF32 and PREF64 conflict"); return -EINVAL; } =20 - if (mem_non_pref_reserve !=3D (uint64_t)-1 && - mem_non_pref_reserve >=3D (1ULL << 32)) { + if (res_reserve.mem_non_pref !=3D (uint64_t)-1 && + res_reserve.mem_non_pref >=3D (1ULL << 32)) { error_setg(errp, "PCI resource reserve cap: mem-reserve must be less tha= n 4G"); return -EINVAL; } =20 - if (mem_pref_32_reserve !=3D (uint64_t)-1 && - mem_pref_32_reserve >=3D (1ULL << 32)) { + if (res_reserve.mem_pref_32 !=3D (uint64_t)-1 && + res_reserve.mem_pref_32 >=3D (1ULL << 32)) { error_setg(errp, "PCI resource reserve cap: pref32-reserve must be less= than 4G"); return -EINVAL; } =20 - if (bus_reserve =3D=3D (uint32_t)-1 && - io_reserve =3D=3D (uint64_t)-1 && - mem_non_pref_reserve =3D=3D (uint64_t)-1 && - mem_pref_32_reserve =3D=3D (uint64_t)-1 && - mem_pref_64_reserve =3D=3D (uint64_t)-1) { + if (res_reserve.bus =3D=3D (uint32_t)-1 && + res_reserve.io =3D=3D (uint64_t)-1 && + res_reserve.mem_non_pref =3D=3D (uint64_t)-1 && + res_reserve.mem_pref_32 =3D=3D (uint64_t)-1 && + res_reserve.mem_pref_64 =3D=3D (uint64_t)-1) { return 0; } =20 @@ -450,11 +446,11 @@ int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, = int cap_offset, PCIBridgeQemuCap cap =3D { .len =3D cap_len, .type =3D REDHAT_PCI_CAP_RESOURCE_RESERVE, - .bus_res =3D bus_reserve, - .io =3D io_reserve, - .mem =3D mem_non_pref_reserve, - .mem_pref_32 =3D mem_pref_32_reserve, - .mem_pref_64 =3D mem_pref_64_reserve + .bus_res =3D res_reserve.bus, + .io =3D res_reserve.io, + .mem =3D res_reserve.mem_non_pref, + .mem_pref_32 =3D res_reserve.mem_pref_32, + .mem_pref_64 =3D res_reserve.mem_pref_64 }; =20 int offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, --=20 MST