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X-Received-From: 2a00:1450:4864:20::12a Subject: [Qemu-devel] [PATCH 08/15] target/xtensa: extract test for cpdisabled exception X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" - add XtensaOpcodeOps::coprocessor with bitmask of coprocessors used by the instruction; - replace coprocessor id parameter of gen_check_cpenable with the bitmask of used coprocessors; - collect coprocessor IDs used by an instruction in the disassembly loop; - put test for coprocessor disabled exception after the alloca test; Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 1 + target/xtensa/translate.c | 230 ++++++++++++++++++++++++------------------= ---- 2 files changed, 123 insertions(+), 108 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index be234958a228..34e5ccd9f1d6 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -381,6 +381,7 @@ typedef struct XtensaOpcodeOps { const uint32_t *par; uint32_t op_flags; uint32_t windowed_register_op; + uint32_t coprocessor; } XtensaOpcodeOps; =20 typedef struct XtensaOpcodeTranslators { diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 9b59f35a1de7..eb123f68b364 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -351,11 +351,12 @@ static bool gen_check_privilege(DisasContext *dc) return false; } =20 -static bool gen_check_cpenable(DisasContext *dc, unsigned cp) +static bool gen_check_cpenable(DisasContext *dc, uint32_t cp_mask) { - if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && - !(dc->cpenable & (1 << cp))) { - gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp); + cp_mask &=3D ~dc->cpenable; + + if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && cp_mask) { + gen_exception_cause(dc, COPROCESSOR0_DISABLED + ctz32(cp_mask)); dc->base.is_jmp =3D DISAS_NORETURN; return false; } @@ -953,6 +954,7 @@ static void disas_xtensa_insn(CPUXtensaState *env, Disa= sContext *dc) } slot_prop[MAX_INSN_SLOTS]; uint32_t debug_cause =3D 0; uint32_t windowed_register =3D 0; + uint32_t coprocessor =3D 0; =20 if (len =3D=3D XTENSA_UNDEFINED) { qemu_log_mask(LOG_GUEST_ERROR, @@ -1050,6 +1052,7 @@ static void disas_xtensa_insn(CPUXtensaState *env, Di= sasContext *dc) reg_opnd ^=3D 1 << i; } } + coprocessor |=3D ops->coprocessor; } =20 if ((op_flags & XTENSA_OP_PRIVILEGED) && @@ -1085,6 +1088,10 @@ static void disas_xtensa_insn(CPUXtensaState *env, D= isasContext *dc) tcg_temp_free(tmp); } =20 + if (coprocessor && !gen_check_cpenable(dc, coprocessor)) { + return; + } + for (slot =3D 0; slot < slots; ++slot) { XtensaOpcodeOps *ops =3D slot_prop[slot].ops; =20 @@ -4084,11 +4091,13 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_rur, .par =3D (const uint32_t[]){FCR}, .windowed_register_op =3D 0x1, + .coprocessor =3D 0x1, }, { .name =3D "rur.fsr", .translate =3D translate_rur, .par =3D (const uint32_t[]){FSR}, .windowed_register_op =3D 0x1, + .coprocessor =3D 0x1, }, { .name =3D "rur.threadptr", .translate =3D translate_rur, @@ -4805,11 +4814,13 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wur, .par =3D (const uint32_t[]){FCR}, .windowed_register_op =3D 0x1, + .coprocessor =3D 0x1, }, { .name =3D "wur.fsr", .translate =3D translate_wur, .par =3D (const uint32_t[]){FSR}, .windowed_register_op =3D 0x1, + .coprocessor =3D 0x1, }, { .name =3D "wur.threadptr", .translate =3D translate_wur, @@ -5354,18 +5365,14 @@ const XtensaOpcodeTranslators xtensa_core_opcodes = =3D { static void translate_abs_s(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_cpenable(dc, 0)) { - gen_helper_abs_s(cpu_FR[arg[0]], cpu_FR[arg[1]]); - } + gen_helper_abs_s(cpu_FR[arg[0]], cpu_FR[arg[1]]); } =20 static void translate_add_s(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_cpenable(dc, 0)) { - gen_helper_add_s(cpu_FR[arg[0]], cpu_env, - cpu_FR[arg[1]], cpu_FR[arg[2]]); - } + gen_helper_add_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[1]], cpu_FR[arg[2]]); } =20 enum { @@ -5391,350 +5398,357 @@ static void translate_compare_s(DisasContext *dc,= const uint32_t arg[], [COMPARE_OLE] =3D gen_helper_ole_s, [COMPARE_ULE] =3D gen_helper_ule_s, }; + TCGv_i32 bit =3D tcg_const_i32(1 << arg[0]); =20 - if (gen_check_cpenable(dc, 0)) { - TCGv_i32 bit =3D tcg_const_i32(1 << arg[0]); - - helper[par[0]](cpu_env, bit, cpu_FR[arg[1]], cpu_FR[arg[2]]); - tcg_temp_free(bit); - } + helper[par[0]](cpu_env, bit, cpu_FR[arg[1]], cpu_FR[arg[2]]); + tcg_temp_free(bit); } =20 static void translate_float_s(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_cpenable(dc, 0)) { - TCGv_i32 scale =3D tcg_const_i32(-arg[2]); + TCGv_i32 scale =3D tcg_const_i32(-arg[2]); =20 - if (par[0]) { - gen_helper_uitof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale= ); - } else { - gen_helper_itof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale); - } - tcg_temp_free(scale); + if (par[0]) { + gen_helper_uitof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale); + } else { + gen_helper_itof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale); } + tcg_temp_free(scale); } =20 static void translate_ftoi_s(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_cpenable(dc, 0)) { - TCGv_i32 rounding_mode =3D tcg_const_i32(par[0]); - TCGv_i32 scale =3D tcg_const_i32(arg[2]); + TCGv_i32 rounding_mode =3D tcg_const_i32(par[0]); + TCGv_i32 scale =3D tcg_const_i32(arg[2]); =20 - if (par[1]) { - gen_helper_ftoui(cpu_R[arg[0]], cpu_FR[arg[1]], - rounding_mode, scale); - } else { - gen_helper_ftoi(cpu_R[arg[0]], cpu_FR[arg[1]], - rounding_mode, scale); - } - tcg_temp_free(rounding_mode); - tcg_temp_free(scale); + if (par[1]) { + gen_helper_ftoui(cpu_R[arg[0]], cpu_FR[arg[1]], + rounding_mode, scale); + } else { + gen_helper_ftoi(cpu_R[arg[0]], cpu_FR[arg[1]], + rounding_mode, scale); } + tcg_temp_free(rounding_mode); + tcg_temp_free(scale); } =20 static void translate_ldsti(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_cpenable(dc, 0)) { - TCGv_i32 addr =3D tcg_temp_new_i32(); + TCGv_i32 addr =3D tcg_temp_new_i32(); =20 - tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); - gen_load_store_alignment(dc, 2, addr, false); - if (par[0]) { - tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring); - } else { - tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring); - } - if (par[1]) { - tcg_gen_mov_i32(cpu_R[arg[1]], addr); - } - tcg_temp_free(addr); + tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + gen_load_store_alignment(dc, 2, addr, false); + if (par[0]) { + tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring); + } else { + tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring); } + if (par[1]) { + tcg_gen_mov_i32(cpu_R[arg[1]], addr); + } + tcg_temp_free(addr); } =20 static void translate_ldstx(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_cpenable(dc, 0)) { - TCGv_i32 addr =3D tcg_temp_new_i32(); + TCGv_i32 addr =3D tcg_temp_new_i32(); =20 - tcg_gen_add_i32(addr, cpu_R[arg[1]], cpu_R[arg[2]]); - gen_load_store_alignment(dc, 2, addr, false); - if (par[0]) { - tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring); - } else { - tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring); - } - if (par[1]) { - tcg_gen_mov_i32(cpu_R[arg[1]], addr); - } - tcg_temp_free(addr); + tcg_gen_add_i32(addr, cpu_R[arg[1]], cpu_R[arg[2]]); + gen_load_store_alignment(dc, 2, addr, false); + if (par[0]) { + tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring); + } else { + tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring); + } + if (par[1]) { + tcg_gen_mov_i32(cpu_R[arg[1]], addr); } + tcg_temp_free(addr); } =20 static void translate_madd_s(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_cpenable(dc, 0)) { - gen_helper_madd_s(cpu_FR[arg[0]], cpu_env, - cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]); - } + gen_helper_madd_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]); } =20 static void translate_mov_s(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_cpenable(dc, 0)) { - tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_FR[arg[1]]); - } + tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_FR[arg[1]]); } =20 static void translate_movcond_s(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_cpenable(dc, 0)) { - TCGv_i32 zero =3D tcg_const_i32(0); + TCGv_i32 zero =3D tcg_const_i32(0); =20 - tcg_gen_movcond_i32(par[0], cpu_FR[arg[0]], - cpu_R[arg[2]], zero, - cpu_FR[arg[1]], cpu_FR[arg[0]]); - tcg_temp_free(zero); - } + tcg_gen_movcond_i32(par[0], cpu_FR[arg[0]], + cpu_R[arg[2]], zero, + cpu_FR[arg[1]], cpu_FR[arg[0]]); + tcg_temp_free(zero); } =20 static void translate_movp_s(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_cpenable(dc, 0)) { - TCGv_i32 zero =3D tcg_const_i32(0); - TCGv_i32 tmp =3D tcg_temp_new_i32(); + TCGv_i32 zero =3D tcg_const_i32(0); + TCGv_i32 tmp =3D tcg_temp_new_i32(); =20 - tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]); - tcg_gen_movcond_i32(par[0], - cpu_FR[arg[0]], tmp, zero, - cpu_FR[arg[1]], cpu_FR[arg[0]]); - tcg_temp_free(tmp); - tcg_temp_free(zero); - } + tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]); + tcg_gen_movcond_i32(par[0], + cpu_FR[arg[0]], tmp, zero, + cpu_FR[arg[1]], cpu_FR[arg[0]]); + tcg_temp_free(tmp); + tcg_temp_free(zero); } =20 static void translate_mul_s(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_cpenable(dc, 0)) { - gen_helper_mul_s(cpu_FR[arg[0]], cpu_env, - cpu_FR[arg[1]], cpu_FR[arg[2]]); - } + gen_helper_mul_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[1]], cpu_FR[arg[2]]); } =20 static void translate_msub_s(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_cpenable(dc, 0)) { - gen_helper_msub_s(cpu_FR[arg[0]], cpu_env, - cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]); - } + gen_helper_msub_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]); } =20 static void translate_neg_s(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_cpenable(dc, 0)) { - gen_helper_neg_s(cpu_FR[arg[0]], cpu_FR[arg[1]]); - } + gen_helper_neg_s(cpu_FR[arg[0]], cpu_FR[arg[1]]); } =20 static void translate_rfr_s(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_cpenable(dc, 0)) { - tcg_gen_mov_i32(cpu_R[arg[0]], cpu_FR[arg[1]]); - } + tcg_gen_mov_i32(cpu_R[arg[0]], cpu_FR[arg[1]]); } =20 static void translate_sub_s(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_cpenable(dc, 0)) { - gen_helper_sub_s(cpu_FR[arg[0]], cpu_env, - cpu_FR[arg[1]], cpu_FR[arg[2]]); - } + gen_helper_sub_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[1]], cpu_FR[arg[2]]); } =20 static void translate_wfr_s(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_cpenable(dc, 0)) { - tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_R[arg[1]]); - } + tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_R[arg[1]]); } =20 static const XtensaOpcodeOps fpu2000_ops[] =3D { { .name =3D "abs.s", .translate =3D translate_abs_s, + .coprocessor =3D 0x1, }, { .name =3D "add.s", .translate =3D translate_add_s, + .coprocessor =3D 0x1, }, { .name =3D "ceil.s", .translate =3D translate_ftoi_s, .par =3D (const uint32_t[]){float_round_up, false}, .windowed_register_op =3D 0x1, + .coprocessor =3D 0x1, }, { .name =3D "float.s", .translate =3D translate_float_s, .par =3D (const uint32_t[]){false}, .windowed_register_op =3D 0x2, + .coprocessor =3D 0x1, }, { .name =3D "floor.s", .translate =3D translate_ftoi_s, .par =3D (const uint32_t[]){float_round_down, false}, .windowed_register_op =3D 0x1, + .coprocessor =3D 0x1, }, { .name =3D "lsi", .translate =3D translate_ldsti, .par =3D (const uint32_t[]){false, false}, .windowed_register_op =3D 0x2, + .coprocessor =3D 0x1, }, { .name =3D "lsiu", .translate =3D translate_ldsti, .par =3D (const uint32_t[]){false, true}, .windowed_register_op =3D 0x2, + .coprocessor =3D 0x1, }, { .name =3D "lsx", .translate =3D translate_ldstx, .par =3D (const uint32_t[]){false, false}, .windowed_register_op =3D 0x6, + .coprocessor =3D 0x1, }, { .name =3D "lsxu", .translate =3D translate_ldstx, .par =3D (const uint32_t[]){false, true}, .windowed_register_op =3D 0x6, + .coprocessor =3D 0x1, }, { .name =3D "madd.s", .translate =3D translate_madd_s, + .coprocessor =3D 0x1, }, { .name =3D "mov.s", .translate =3D translate_mov_s, + .coprocessor =3D 0x1, }, { .name =3D "moveqz.s", .translate =3D translate_movcond_s, .par =3D (const uint32_t[]){TCG_COND_EQ}, .windowed_register_op =3D 0x4, + .coprocessor =3D 0x1, }, { .name =3D "movf.s", .translate =3D translate_movp_s, .par =3D (const uint32_t[]){TCG_COND_EQ}, + .coprocessor =3D 0x1, }, { .name =3D "movgez.s", .translate =3D translate_movcond_s, .par =3D (const uint32_t[]){TCG_COND_GE}, .windowed_register_op =3D 0x4, + .coprocessor =3D 0x1, }, { .name =3D "movltz.s", .translate =3D translate_movcond_s, .par =3D (const uint32_t[]){TCG_COND_LT}, .windowed_register_op =3D 0x4, + .coprocessor =3D 0x1, }, { .name =3D "movnez.s", .translate =3D translate_movcond_s, .par =3D (const uint32_t[]){TCG_COND_NE}, .windowed_register_op =3D 0x4, + .coprocessor =3D 0x1, }, { .name =3D "movt.s", .translate =3D translate_movp_s, .par =3D (const uint32_t[]){TCG_COND_NE}, + .coprocessor =3D 0x1, }, { .name =3D "msub.s", .translate =3D translate_msub_s, + .coprocessor =3D 0x1, }, { .name =3D "mul.s", .translate =3D translate_mul_s, + .coprocessor =3D 0x1, }, { .name =3D "neg.s", .translate =3D translate_neg_s, + .coprocessor =3D 0x1, }, { .name =3D "oeq.s", .translate =3D translate_compare_s, .par =3D (const uint32_t[]){COMPARE_OEQ}, + .coprocessor =3D 0x1, }, { .name =3D "ole.s", .translate =3D translate_compare_s, .par =3D (const uint32_t[]){COMPARE_OLE}, + .coprocessor =3D 0x1, }, { .name =3D "olt.s", .translate =3D translate_compare_s, .par =3D (const uint32_t[]){COMPARE_OLT}, + .coprocessor =3D 0x1, }, { .name =3D "rfr", .translate =3D translate_rfr_s, .windowed_register_op =3D 0x1, + .coprocessor =3D 0x1, }, { .name =3D "round.s", .translate =3D translate_ftoi_s, .par =3D (const uint32_t[]){float_round_nearest_even, false}, .windowed_register_op =3D 0x1, + .coprocessor =3D 0x1, }, { .name =3D "ssi", .translate =3D translate_ldsti, .par =3D (const uint32_t[]){true, false}, .windowed_register_op =3D 0x2, + .coprocessor =3D 0x1, }, { .name =3D "ssiu", .translate =3D translate_ldsti, .par =3D (const uint32_t[]){true, true}, .windowed_register_op =3D 0x2, + .coprocessor =3D 0x1, }, { .name =3D "ssx", .translate =3D translate_ldstx, .par =3D (const uint32_t[]){true, false}, .windowed_register_op =3D 0x6, + .coprocessor =3D 0x1, }, { .name =3D "ssxu", .translate =3D translate_ldstx, .par =3D (const uint32_t[]){true, true}, .windowed_register_op =3D 0x6, + .coprocessor =3D 0x1, }, { .name =3D "sub.s", .translate =3D translate_sub_s, + .coprocessor =3D 0x1, }, { .name =3D "trunc.s", .translate =3D translate_ftoi_s, .par =3D (const uint32_t[]){float_round_to_zero, false}, .windowed_register_op =3D 0x1, + .coprocessor =3D 0x1, }, { .name =3D "ueq.s", .translate =3D translate_compare_s, .par =3D (const uint32_t[]){COMPARE_UEQ}, + .coprocessor =3D 0x1, }, { .name =3D "ufloat.s", .translate =3D translate_float_s, .par =3D (const uint32_t[]){true}, .windowed_register_op =3D 0x2, + .coprocessor =3D 0x1, }, { .name =3D "ule.s", .translate =3D translate_compare_s, .par =3D (const uint32_t[]){COMPARE_ULE}, + .coprocessor =3D 0x1, }, { .name =3D "ult.s", .translate =3D translate_compare_s, .par =3D (const uint32_t[]){COMPARE_ULT}, + .coprocessor =3D 0x1, }, { .name =3D "un.s", .translate =3D translate_compare_s, .par =3D (const uint32_t[]){COMPARE_UN}, + .coprocessor =3D 0x1, }, { .name =3D "utrunc.s", .translate =3D translate_ftoi_s, .par =3D (const uint32_t[]){float_round_to_zero, true}, .windowed_register_op =3D 0x1, + .coprocessor =3D 0x1, }, { .name =3D "wfr", .translate =3D translate_wfr_s, .windowed_register_op =3D 0x2, + .coprocessor =3D 0x1, }, }; =20 --=20 2.11.0