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X-Received-From: 2a00:1450:4864:20::144 Subject: [Qemu-devel] [PATCH 02/15] target/xtensa: extract test for privileged instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" - mark privileged instructions; - put single privileged instruction check after disassembly loop; - translate_[di]cache: drop parameter 0, shift parameters one down; Signed-off-by: Max Filippov --- target/xtensa/translate.c | 387 +++++++++++++++++++++++++++++++++++-------= ---- 1 file changed, 294 insertions(+), 93 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 8c6d1e79866c..ebee7bd65e48 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1042,6 +1042,11 @@ static void disas_xtensa_insn(CPUXtensaState *env, D= isasContext *dc) } } =20 + if ((op_flags & XTENSA_OP_PRIVILEGED) && + !gen_check_privilege(dc)) { + return; + } + for (slot =3D 0; slot < slots; ++slot) { XtensaOpcodeOps *ops =3D slot_prop[slot].ops; =20 @@ -1584,12 +1589,11 @@ static void translate_const16(DisasContext *dc, con= st uint32_t arg[], } } =20 -/* par[0]: privileged, par[1]: check memory access */ +/* par[0]: check memory access */ static void translate_dcache(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if ((!par[0] || gen_check_privilege(dc)) && - gen_window_check1(dc, arg[0]) && par[1]) { + if (gen_window_check1(dc, arg[0]) && par[0]) { TCGv_i32 addr =3D tcg_temp_new_i32(); TCGv_i32 res =3D tcg_temp_new_i32(); =20 @@ -1648,12 +1652,11 @@ static void translate_extui(DisasContext *dc, const= uint32_t arg[], } } =20 -/* par[0]: privileged, par[1]: check memory access */ +/* par[0]: check memory access */ static void translate_icache(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if ((!par[0] || gen_check_privilege(dc)) && - gen_window_check1(dc, arg[0]) && par[1]) { + if (gen_window_check1(dc, arg[0]) && par[0]) { #ifndef CONFIG_USER_ONLY TCGv_i32 addr =3D tcg_temp_new_i32(); =20 @@ -1668,8 +1671,7 @@ static void translate_icache(DisasContext *dc, const = uint32_t arg[], static void translate_itlb(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_privilege(dc) && - gen_window_check1(dc, arg[0])) { + if (gen_window_check1(dc, arg[0])) { #ifndef CONFIG_USER_ONLY TCGv_i32 dtlb =3D tcg_const_i32(par[0]); =20 @@ -1698,8 +1700,7 @@ static void translate_jx(DisasContext *dc, const uint= 32_t arg[], static void translate_l32e(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_privilege(dc) && - gen_window_check2(dc, arg[0], arg[1])) { + if (gen_window_check2(dc, arg[0], arg[1])) { TCGv_i32 addr =3D tcg_temp_new_i32(); =20 tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); @@ -2061,8 +2062,7 @@ static void translate_or(DisasContext *dc, const uint= 32_t arg[], static void translate_ptlb(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_privilege(dc) && - gen_window_check2(dc, arg[0], arg[1])) { + if (gen_window_check2(dc, arg[0], arg[1])) { #ifndef CONFIG_USER_ONLY TCGv_i32 dtlb =3D tcg_const_i32(par[0]); =20 @@ -2137,8 +2137,7 @@ static void translate_read_impwire(DisasContext *dc, = const uint32_t arg[], static void translate_rer(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_privilege(dc) && - gen_window_check2(dc, arg[0], arg[1])) { + if (gen_window_check2(dc, arg[0], arg[1])) { gen_helper_rer(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]]); } } @@ -2177,73 +2176,62 @@ static void translate_retw(DisasContext *dc, const = uint32_t arg[], static void translate_rfde(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_privilege(dc)) { - gen_jump(dc, cpu_SR[dc->config->ndepc ? DEPC : EPC1]); - } + gen_jump(dc, cpu_SR[dc->config->ndepc ? DEPC : EPC1]); } =20 static void translate_rfe(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_privilege(dc)) { - tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); - gen_check_interrupts(dc); - gen_jump(dc, cpu_SR[EPC1]); - } + tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); + gen_check_interrupts(dc); + gen_jump(dc, cpu_SR[EPC1]); } =20 static void translate_rfi(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_privilege(dc)) { - tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0] - 2]); - gen_check_interrupts(dc); - gen_jump(dc, cpu_SR[EPC1 + arg[0] - 1]); - } + tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0] - 2]); + gen_check_interrupts(dc); + gen_jump(dc, cpu_SR[EPC1 + arg[0] - 1]); } =20 static void translate_rfw(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_privilege(dc)) { - TCGv_i32 tmp =3D tcg_const_i32(1); + TCGv_i32 tmp =3D tcg_const_i32(1); =20 - tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); - tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]); + tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); + tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]); =20 - if (par[0]) { - tcg_gen_andc_i32(cpu_SR[WINDOW_START], - cpu_SR[WINDOW_START], tmp); - } else { - tcg_gen_or_i32(cpu_SR[WINDOW_START], - cpu_SR[WINDOW_START], tmp); - } + if (par[0]) { + tcg_gen_andc_i32(cpu_SR[WINDOW_START], + cpu_SR[WINDOW_START], tmp); + } else { + tcg_gen_or_i32(cpu_SR[WINDOW_START], + cpu_SR[WINDOW_START], tmp); + } =20 - gen_helper_restore_owb(cpu_env); - gen_check_interrupts(dc); - gen_jump(dc, cpu_SR[EPC1]); + gen_helper_restore_owb(cpu_env); + gen_check_interrupts(dc); + gen_jump(dc, cpu_SR[EPC1]); =20 - tcg_temp_free(tmp); - } + tcg_temp_free(tmp); } =20 static void translate_rotw(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_privilege(dc)) { - TCGv_i32 tmp =3D tcg_const_i32(arg[0]); - gen_helper_rotw(cpu_env, tmp); - tcg_temp_free(tmp); - /* This can change tb->flags, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); - } + TCGv_i32 tmp =3D tcg_const_i32(arg[0]); + gen_helper_rotw(cpu_env, tmp); + tcg_temp_free(tmp); + /* This can change tb->flags, so exit tb */ + gen_jumpi_check_loop_end(dc, -1); } =20 static void translate_rsil(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_privilege(dc) && - gen_window_check1(dc, arg[0])) { + if (gen_window_check1(dc, arg[0])) { tcg_gen_mov_i32(cpu_R[arg[0]], cpu_SR[PS]); tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1]); @@ -2261,8 +2249,7 @@ static bool test_ill_rsr(DisasContext *dc, const uint= 32_t arg[], static void translate_rsr(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if ((par[0] < 64 || gen_check_privilege(dc)) && - gen_window_check1(dc, arg[0])) { + if (gen_window_check1(dc, arg[0])) { if (gen_rsr(dc, cpu_R[arg[0]], par[0])) { gen_jumpi_check_loop_end(dc, 0); } @@ -2272,21 +2259,20 @@ static void translate_rsr(DisasContext *dc, const u= int32_t arg[], static void translate_rtlb(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { +#ifndef CONFIG_USER_ONLY static void (* const helper[])(TCGv_i32 r, TCGv_env env, TCGv_i32 a1, TCGv_i32 a2) =3D { -#ifndef CONFIG_USER_ONLY gen_helper_rtlb0, gen_helper_rtlb1, -#endif }; =20 - if (gen_check_privilege(dc) && - gen_window_check2(dc, arg[0], arg[1])) { + if (gen_window_check2(dc, arg[0], arg[1])) { TCGv_i32 dtlb =3D tcg_const_i32(par[0]); =20 helper[par[1]](cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb); tcg_temp_free(dtlb); } +#endif } =20 static void translate_rur(DisasContext *dc, const uint32_t arg[], @@ -2343,8 +2329,7 @@ static void translate_s32c1i(DisasContext *dc, const = uint32_t arg[], static void translate_s32e(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_privilege(dc) && - gen_window_check2(dc, arg[0], arg[1])) { + if (gen_window_check2(dc, arg[0], arg[1])) { TCGv_i32 addr =3D tcg_temp_new_i32(); =20 tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); @@ -2401,9 +2386,7 @@ static void translate_simcall(DisasContext *dc, const= uint32_t arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY - if (gen_check_privilege(dc)) { - gen_helper_simcall(cpu_env); - } + gen_helper_simcall(cpu_env); #endif } =20 @@ -2583,18 +2566,15 @@ static void translate_syscall(DisasContext *dc, con= st uint32_t arg[], static void translate_waiti(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_privilege(dc)) { #ifndef CONFIG_USER_ONLY - gen_waiti(dc, arg[0]); + gen_waiti(dc, arg[0]); #endif - } } =20 static void translate_wtlb(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_privilege(dc) && - gen_window_check2(dc, arg[0], arg[1])) { + if (gen_window_check2(dc, arg[0], arg[1])) { #ifndef CONFIG_USER_ONLY TCGv_i32 dtlb =3D tcg_const_i32(par[0]); =20 @@ -2609,8 +2589,7 @@ static void translate_wtlb(DisasContext *dc, const ui= nt32_t arg[], static void translate_wer(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_check_privilege(dc) && - gen_window_check2(dc, arg[0], arg[1])) { + if (gen_window_check2(dc, arg[0], arg[1])) { gen_helper_wer(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]]); } } @@ -2633,8 +2612,7 @@ static bool test_ill_wsr(DisasContext *dc, const uint= 32_t arg[], static void translate_wsr(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if ((par[0] < 64 || gen_check_privilege(dc)) && - gen_window_check1(dc, arg[0])) { + if (gen_window_check1(dc, arg[0])) { gen_wsr(dc, par[0], cpu_R[arg[0]]); } } @@ -2668,8 +2646,7 @@ static bool test_ill_xsr(DisasContext *dc, const uint= 32_t arg[], static void translate_xsr(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if ((par[0] < 64 || gen_check_privilege(dc)) && - gen_window_check1(dc, arg[0])) { + if (gen_window_check1(dc, arg[0])) { TCGv_i32 tmp =3D tcg_temp_new_i32(); bool rsr_end, wsr_end; =20 @@ -2906,55 +2883,62 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "dhi", .translate =3D translate_dcache, - .par =3D (const uint32_t[]){true, true}, + .par =3D (const uint32_t[]){true}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "dhu", .translate =3D translate_dcache, - .par =3D (const uint32_t[]){true, true}, + .par =3D (const uint32_t[]){true}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "dhwb", .translate =3D translate_dcache, - .par =3D (const uint32_t[]){false, true}, + .par =3D (const uint32_t[]){true}, }, { .name =3D "dhwbi", .translate =3D translate_dcache, - .par =3D (const uint32_t[]){false, true}, + .par =3D (const uint32_t[]){true}, }, { .name =3D "dii", .translate =3D translate_dcache, - .par =3D (const uint32_t[]){true, false}, + .par =3D (const uint32_t[]){false}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "diu", .translate =3D translate_dcache, - .par =3D (const uint32_t[]){true, false}, + .par =3D (const uint32_t[]){false}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "diwb", .translate =3D translate_dcache, - .par =3D (const uint32_t[]){true, false}, + .par =3D (const uint32_t[]){false}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "diwbi", .translate =3D translate_dcache, - .par =3D (const uint32_t[]){true, false}, + .par =3D (const uint32_t[]){false}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "dpfl", .translate =3D translate_dcache, - .par =3D (const uint32_t[]){true, true}, + .par =3D (const uint32_t[]){true}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "dpfr", .translate =3D translate_dcache, - .par =3D (const uint32_t[]){false, false}, + .par =3D (const uint32_t[]){false}, }, { .name =3D "dpfro", .translate =3D translate_dcache, - .par =3D (const uint32_t[]){false, false}, + .par =3D (const uint32_t[]){false}, }, { .name =3D "dpfw", .translate =3D translate_dcache, - .par =3D (const uint32_t[]){false, false}, + .par =3D (const uint32_t[]){false}, }, { .name =3D "dpfwo", .translate =3D translate_dcache, - .par =3D (const uint32_t[]){false, false}, + .par =3D (const uint32_t[]){false}, }, { .name =3D "dsync", .translate =3D translate_nop, @@ -2984,26 +2968,31 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "idtlb", .translate =3D translate_itlb, .par =3D (const uint32_t[]){true}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "ihi", .translate =3D translate_icache, - .par =3D (const uint32_t[]){false, true}, + .par =3D (const uint32_t[]){true}, }, { .name =3D "ihu", .translate =3D translate_icache, - .par =3D (const uint32_t[]){true, true}, + .par =3D (const uint32_t[]){true}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "iii", .translate =3D translate_icache, - .par =3D (const uint32_t[]){true, false}, + .par =3D (const uint32_t[]){false}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "iitlb", .translate =3D translate_itlb, .par =3D (const uint32_t[]){false}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "iiu", .translate =3D translate_icache, - .par =3D (const uint32_t[]){true, false}, + .par =3D (const uint32_t[]){false}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "ill", .op_flags =3D XTENSA_OP_ILL, @@ -3013,11 +3002,12 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "ipf", .translate =3D translate_icache, - .par =3D (const uint32_t[]){false, false}, + .par =3D (const uint32_t[]){false}, }, { .name =3D "ipfl", .translate =3D translate_icache, - .par =3D (const uint32_t[]){true, true}, + .par =3D (const uint32_t[]){true}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "isync", .translate =3D translate_nop, @@ -3042,6 +3032,7 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "l32e", .translate =3D translate_l32e, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "l32i", .translate =3D translate_ldst, @@ -3439,10 +3430,12 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "pdtlb", .translate =3D translate_ptlb, .par =3D (const uint32_t[]){true}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "pitlb", .translate =3D translate_ptlb, .par =3D (const uint32_t[]){false}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "quos", .translate =3D translate_quos, @@ -3455,10 +3448,12 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "rdtlb0", .translate =3D translate_rtlb, .par =3D (const uint32_t[]){true, 0}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rdtlb1", .translate =3D translate_rtlb, .par =3D (const uint32_t[]){true, 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "read_impwire", .translate =3D translate_read_impwire, @@ -3473,6 +3468,7 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "rer", .translate =3D translate_rer, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "ret", .translate =3D translate_ret, @@ -3493,47 +3489,58 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "rfde", .translate =3D translate_rfde, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rfdo", .op_flags =3D XTENSA_OP_ILL, }, { .name =3D "rfe", .translate =3D translate_rfe, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rfi", .translate =3D translate_rfi, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rfwo", .translate =3D translate_rfw, .par =3D (const uint32_t[]){true}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rfwu", .translate =3D translate_rfw, .par =3D (const uint32_t[]){false}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "ritlb0", .translate =3D translate_rtlb, .par =3D (const uint32_t[]){false, 0}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "ritlb1", .translate =3D translate_rtlb, .par =3D (const uint32_t[]){false, 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rotw", .translate =3D translate_rotw, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsil", .translate =3D translate_rsil, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.176", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){176}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.208", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){208}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.acchi", .translate =3D translate_rsr, @@ -3549,6 +3556,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){ATOMCTL}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.br", .translate =3D translate_rsr, @@ -3559,241 +3567,289 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){CACHEATTR}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ccompare0", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){CCOMPARE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ccompare1", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){CCOMPARE + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ccompare2", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){CCOMPARE + 2}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ccount", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){CCOUNT}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.configid0", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){CONFIGID0}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.configid1", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){CONFIGID1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.cpenable", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){CPENABLE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.dbreaka0", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){DBREAKA}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.dbreaka1", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){DBREAKA + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.dbreakc0", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){DBREAKC}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.dbreakc1", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){DBREAKC + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ddr", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){DDR}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.debugcause", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){DEBUGCAUSE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.depc", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){DEPC}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.dtlbcfg", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){DTLBCFG}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.epc1", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPC1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.epc2", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPC1 + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.epc3", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPC1 + 2}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.epc4", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPC1 + 3}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.epc5", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPC1 + 4}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.epc6", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPC1 + 5}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.epc7", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPC1 + 6}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.eps2", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPS2}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.eps3", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPS2 + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.eps4", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPS2 + 2}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.eps5", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPS2 + 3}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.eps6", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPS2 + 4}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.eps7", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPS2 + 5}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.exccause", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EXCCAUSE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.excsave1", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EXCSAVE1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.excsave2", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EXCSAVE1 + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.excsave3", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EXCSAVE1 + 2}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.excsave4", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EXCSAVE1 + 3}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.excsave5", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EXCSAVE1 + 4}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.excsave6", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EXCSAVE1 + 5}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.excsave7", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EXCSAVE1 + 6}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.excvaddr", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EXCVADDR}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ibreaka0", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){IBREAKA}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ibreaka1", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){IBREAKA + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ibreakenable", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){IBREAKENABLE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.icount", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){ICOUNT}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.icountlevel", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){ICOUNTLEVEL}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.intclear", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){INTCLEAR}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.intenable", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){INTENABLE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.interrupt", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){INTSET}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.intset", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){INTSET}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.itlbcfg", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){ITLBCFG}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.lbeg", .translate =3D translate_rsr, @@ -3839,46 +3895,55 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){MEMCTL}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.misc0", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){MISC}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.misc1", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){MISC + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.misc2", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){MISC + 2}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.misc3", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){MISC + 3}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.prid", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){PRID}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ps", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){PS}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.ptevaddr", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){PTEVADDR}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.rasid", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){RASID}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.sar", .translate =3D translate_rsr, @@ -3894,16 +3959,19 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){VECBASE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.windowbase", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){WINDOW_BASE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsr.windowstart", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){WINDOW_START}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "rsync", .translate =3D translate_nop, @@ -3933,6 +4001,7 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "s32e", .translate =3D translate_s32e, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "s32i", .translate =3D translate_ldst, @@ -3971,6 +4040,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "simcall", .translate =3D translate_simcall, .test_ill =3D test_ill_simcall, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "sll", .translate =3D translate_sll, @@ -4044,17 +4114,21 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "waiti", .translate =3D translate_waiti, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wdtlb", .translate =3D translate_wtlb, .par =3D (const uint32_t[]){true}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wer", .translate =3D translate_wer, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "witlb", .translate =3D translate_wtlb, .par =3D (const uint32_t[]){false}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wrmsk_expstate", .translate =3D translate_wrmsk_expstate, @@ -4063,11 +4137,13 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){176}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.208", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){208}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.acchi", .translate =3D translate_wsr, @@ -4083,6 +4159,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){ATOMCTL}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.br", .translate =3D translate_wsr, @@ -4093,241 +4170,289 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CACHEATTR}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.ccompare0", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CCOMPARE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.ccompare1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CCOMPARE + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.ccompare2", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CCOMPARE + 2}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.ccount", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CCOUNT}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.configid0", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CONFIGID0}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.configid1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CONFIGID1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.cpenable", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CPENABLE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.dbreaka0", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){DBREAKA}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.dbreaka1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){DBREAKA + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.dbreakc0", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){DBREAKC}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.dbreakc1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){DBREAKC + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.ddr", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){DDR}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.debugcause", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){DEBUGCAUSE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.depc", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){DEPC}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.dtlbcfg", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){DTLBCFG}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.epc1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPC1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.epc2", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPC1 + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.epc3", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPC1 + 2}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.epc4", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPC1 + 3}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.epc5", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPC1 + 4}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.epc6", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPC1 + 5}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.epc7", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPC1 + 6}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.eps2", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPS2}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.eps3", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPS2 + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.eps4", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPS2 + 2}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.eps5", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPS2 + 3}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.eps6", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPS2 + 4}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.eps7", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPS2 + 5}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.exccause", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EXCCAUSE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.excsave1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EXCSAVE1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.excsave2", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EXCSAVE1 + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.excsave3", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EXCSAVE1 + 2}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.excsave4", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EXCSAVE1 + 3}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.excsave5", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EXCSAVE1 + 4}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.excsave6", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EXCSAVE1 + 5}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.excsave7", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EXCSAVE1 + 6}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.excvaddr", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EXCVADDR}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.ibreaka0", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){IBREAKA}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.ibreaka1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){IBREAKA + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.ibreakenable", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){IBREAKENABLE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.icount", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){ICOUNT}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.icountlevel", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){ICOUNTLEVEL}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.intclear", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){INTCLEAR}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.intenable", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){INTENABLE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.interrupt", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){INTSET}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.intset", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){INTSET}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.itlbcfg", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){ITLBCFG}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.lbeg", .translate =3D translate_wsr, @@ -4373,51 +4498,61 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){MEMCTL}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.misc0", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){MISC}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.misc1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){MISC + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.misc2", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){MISC + 2}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.misc3", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){MISC + 3}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.mmid", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){MMID}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.prid", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){PRID}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.ps", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){PS}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.ptevaddr", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){PTEVADDR}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.rasid", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){RASID}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.sar", .translate =3D translate_wsr, @@ -4433,16 +4568,19 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){VECBASE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.windowbase", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){WINDOW_BASE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wsr.windowstart", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){WINDOW_START}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "wur.expstate", .translate =3D translate_wur, @@ -4471,11 +4609,13 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){176}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.208", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){208}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.acchi", .translate =3D translate_xsr, @@ -4491,6 +4631,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){ATOMCTL}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.br", .translate =3D translate_xsr, @@ -4501,241 +4642,289 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CACHEATTR}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.ccompare0", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CCOMPARE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.ccompare1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CCOMPARE + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.ccompare2", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CCOMPARE + 2}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.ccount", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CCOUNT}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.configid0", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CONFIGID0}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.configid1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CONFIGID1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.cpenable", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CPENABLE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.dbreaka0", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){DBREAKA}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.dbreaka1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){DBREAKA + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.dbreakc0", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){DBREAKC}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.dbreakc1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){DBREAKC + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.ddr", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){DDR}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.debugcause", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){DEBUGCAUSE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.depc", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){DEPC}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.dtlbcfg", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){DTLBCFG}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.epc1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPC1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.epc2", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPC1 + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.epc3", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPC1 + 2}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.epc4", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPC1 + 3}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.epc5", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPC1 + 4}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.epc6", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPC1 + 5}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.epc7", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPC1 + 6}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.eps2", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPS2}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.eps3", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPS2 + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.eps4", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPS2 + 2}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.eps5", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPS2 + 3}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.eps6", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPS2 + 4}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.eps7", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPS2 + 5}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.exccause", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EXCCAUSE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.excsave1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EXCSAVE1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.excsave2", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EXCSAVE1 + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.excsave3", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EXCSAVE1 + 2}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.excsave4", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EXCSAVE1 + 3}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.excsave5", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EXCSAVE1 + 4}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.excsave6", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EXCSAVE1 + 5}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.excsave7", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EXCSAVE1 + 6}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.excvaddr", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EXCVADDR}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.ibreaka0", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){IBREAKA}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.ibreaka1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){IBREAKA + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.ibreakenable", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){IBREAKENABLE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.icount", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){ICOUNT}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.icountlevel", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){ICOUNTLEVEL}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.intclear", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){INTCLEAR}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.intenable", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){INTENABLE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.interrupt", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){INTSET}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.intset", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){INTSET}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.itlbcfg", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){ITLBCFG}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.lbeg", .translate =3D translate_xsr, @@ -4781,46 +4970,55 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){MEMCTL}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.misc0", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){MISC}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.misc1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){MISC + 1}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.misc2", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){MISC + 2}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.misc3", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){MISC + 3}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.prid", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){PRID}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.ps", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){PS}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.ptevaddr", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){PTEVADDR}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.rasid", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){RASID}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.sar", .translate =3D translate_xsr, @@ -4836,16 +5034,19 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){VECBASE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.windowbase", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){WINDOW_BASE}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, { .name =3D "xsr.windowstart", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){WINDOW_START}, + .op_flags =3D XTENSA_OP_PRIVILEGED, }, }; =20 --=20 2.11.0