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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id g10-v6sm59337lfl.11.2018.09.04.18.44.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Sep 2018 18:44:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YEc5WRdgqIzKSKPfiT77xaz6rVLqgh4O4TAoqikAMZw=; b=RwW/Zylj/+MaVdaYKXA33DOSD1bO0/cT0ZzytkP9FnGZvc8xtZScsjDn4Tw1s3xnr9 FII+Bn4/SdYRR15m/6Q/Y753XkRgWID5mHMSWaWPtKyGTv2GRiUrwQ2gSiR+NeaAnUeI NONaCSdORfrOJrSjhA354iv4s2wVpH5MKN/YcoYUlvncNiihkvsgWXlbLIjalxcsLv9g cLFQc1SIoRtcL+ts8XNUzUNLa28R2gG1hMzFCa4044ASXheyGqxvhQpYBTpLVBZ4pF5l 5Ixip8pEqPO0BOP0cS/flXOlVulkQqKIhY2iSazZWi3NoxPsBKzUx+vtevkQolCyqZNa l+eQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YEc5WRdgqIzKSKPfiT77xaz6rVLqgh4O4TAoqikAMZw=; b=oALW6NF619y5OQSeiiT63I4akPuYaMdCZFnY3TqkE0i6Fax+kTK0EfAG/ShPNljLSj Un/2wMy+VivsiGTsfW1w7KgH+fDVUFQzLuy/qoLqVJUV0xgcTv32Ns5z7OZ7P5p/NKUJ nZdgcPaYrqCEwsRwuh5EE7YpOyT0Z7iSm/lT+vAkezDXgMQVBTgT4Xt0aDTSqFxc1/O8 ZtdLceHWQAhPEJu9ipcxOEjHV6ZP3yY7u+EbtYlMHqosjbBX28rnGqk/I162KpkWLMeP mXNc7GHZyrbF/2gGv7UqjjpcxO59N7rGYernKYzCSeMTC4VljVnG7gMthqZ1UuFeM45x HeFA== X-Gm-Message-State: APzg51BEu+OebZWSg3xdsWOqOdHRa0trCDhi60DiMjqpkgRGOmZ+hh3Z K9lmFEH0Nu1OFZtHuuSkFwldmSxzzBk= X-Google-Smtp-Source: ANB0VdZRypZ+ecXnKYboSg5Cb+9p55Pu+kDhLLUY/8FODzgRjW3cwejwQBUlWc5ikzCEizcI/+/TRw== X-Received: by 2002:a19:4e4e:: with SMTP id c75-v6mr21687407lfb.116.1536111893058; Tue, 04 Sep 2018 18:44:53 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Tue, 4 Sep 2018 18:43:52 -0700 Message-Id: <20180905014352.970-16-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180905014352.970-1-jcmvbkbc@gmail.com> References: <20180905014352.970-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::141 Subject: [Qemu-devel] [PATCH 15/15] target/xtensa: extract gen_check_interrupts call X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" - mark instructions that affect active IRQ level; - put call for gen_check_interrupts right after the instruction translation; when FLIX is enabled it will need to appear before other exits from the TB as well; Signed-off-by: Max Filippov --- target/xtensa/translate.c | 78 ++++++++++++++++++++++++++++++++-----------= ---- 1 file changed, 53 insertions(+), 25 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 19a829286d22..7e4eedca4d34 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -660,7 +660,6 @@ static void gen_wsr_intset(DisasContext *dc, uint32_t s= r, TCGv_i32 v) { tcg_gen_andi_i32(cpu_SR[sr], v, dc->config->inttype_mask[INTTYPE_SOFTWARE]); - gen_check_interrupts(dc); } =20 static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v) @@ -673,13 +672,11 @@ static void gen_wsr_intclear(DisasContext *dc, uint32= _t sr, TCGv_i32 v) dc->config->inttype_mask[INTTYPE_SOFTWARE]); tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp); tcg_temp_free(tmp); - gen_check_interrupts(dc); } =20 static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) { tcg_gen_mov_i32(cpu_SR[sr], v); - gen_check_interrupts(dc); } =20 static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v) @@ -691,7 +688,6 @@ static void gen_wsr_ps(DisasContext *dc, uint32_t sr, T= CGv_i32 v) mask |=3D PS_RING; } tcg_gen_andi_i32(cpu_SR[sr], v, mask); - gen_check_interrupts(dc); } =20 static void gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v) @@ -1053,6 +1049,10 @@ static void disas_xtensa_insn(CPUXtensaState *env, D= isasContext *dc) } =20 if (dc->base.is_jmp =3D=3D DISAS_NEXT) { + if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) { + gen_check_interrupts(dc); + } + if (op_flags & XTENSA_OP_EXIT_TB_M1) { /* Change in mmu index, memory mapping or tb->flags; exit tb */ gen_jumpi_check_loop_end(dc, -1); @@ -2064,7 +2064,6 @@ static void translate_rfe(DisasContext *dc, const uin= t32_t arg[], const uint32_t par[]) { tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); - gen_check_interrupts(dc); gen_jump(dc, cpu_SR[EPC1]); } =20 @@ -2072,7 +2071,6 @@ static void translate_rfi(DisasContext *dc, const uin= t32_t arg[], const uint32_t par[]) { tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0] - 2]); - gen_check_interrupts(dc); gen_jump(dc, cpu_SR[EPC1 + arg[0] - 1]); } =20 @@ -2092,11 +2090,9 @@ static void translate_rfw(DisasContext *dc, const ui= nt32_t arg[], cpu_SR[WINDOW_START], tmp); } =20 + tcg_temp_free(tmp); gen_helper_restore_owb(cpu_env); - gen_check_interrupts(dc); gen_jump(dc, cpu_SR[EPC1]); - - tcg_temp_free(tmp); } =20 static void translate_rotw(DisasContext *dc, const uint32_t arg[], @@ -2113,7 +2109,6 @@ static void translate_rsil(DisasContext *dc, const ui= nt32_t arg[], tcg_gen_mov_i32(cpu_R[arg[0]], cpu_SR[PS]); tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1]); - gen_check_interrupts(dc); } =20 static bool test_ill_rsr(DisasContext *dc, const uint32_t arg[], @@ -3464,21 +3459,21 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "rfe", .translate =3D translate_rfe, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS, }, { .name =3D "rfi", .translate =3D translate_rfi, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS, }, { .name =3D "rfwo", .translate =3D translate_rfw, .par =3D (const uint32_t[]){true}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS, }, { .name =3D "rfwu", .translate =3D translate_rfw, .par =3D (const uint32_t[]){false}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS, }, { .name =3D "ritlb0", .translate =3D translate_rtlb, @@ -3498,7 +3493,10 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "rsil", .translate =3D translate_rsil, - .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, + .op_flags =3D + XTENSA_OP_PRIVILEGED | + XTENSA_OP_EXIT_TB_0 | + XTENSA_OP_CHECK_INTERRUPTS, .windowed_register_op =3D 0x1, }, { .name =3D "rsr.176", @@ -4564,28 +4562,40 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){INTCLEAR}, - .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, + .op_flags =3D + XTENSA_OP_PRIVILEGED | + XTENSA_OP_EXIT_TB_0 | + XTENSA_OP_CHECK_INTERRUPTS, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.intenable", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){INTENABLE}, - .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, + .op_flags =3D + XTENSA_OP_PRIVILEGED | + XTENSA_OP_EXIT_TB_0 | + XTENSA_OP_CHECK_INTERRUPTS, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.interrupt", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){INTSET}, - .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, + .op_flags =3D + XTENSA_OP_PRIVILEGED | + XTENSA_OP_EXIT_TB_0 | + XTENSA_OP_CHECK_INTERRUPTS, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.intset", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){INTSET}, - .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, + .op_flags =3D + XTENSA_OP_PRIVILEGED | + XTENSA_OP_EXIT_TB_0 | + XTENSA_OP_CHECK_INTERRUPTS, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.itlbcfg", @@ -4699,7 +4709,10 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){PS}, - .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, + .op_flags =3D + XTENSA_OP_PRIVILEGED | + XTENSA_OP_EXIT_TB_M1 | + XTENSA_OP_CHECK_INTERRUPTS, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.ptevaddr", @@ -5123,28 +5136,40 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){INTCLEAR}, - .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, + .op_flags =3D + XTENSA_OP_PRIVILEGED | + XTENSA_OP_EXIT_TB_0 | + XTENSA_OP_CHECK_INTERRUPTS, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.intenable", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){INTENABLE}, - .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, + .op_flags =3D + XTENSA_OP_PRIVILEGED | + XTENSA_OP_EXIT_TB_0 | + XTENSA_OP_CHECK_INTERRUPTS, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.interrupt", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){INTSET}, - .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, + .op_flags =3D + XTENSA_OP_PRIVILEGED | + XTENSA_OP_EXIT_TB_0 | + XTENSA_OP_CHECK_INTERRUPTS, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.intset", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){INTSET}, - .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, + .op_flags =3D + XTENSA_OP_PRIVILEGED | + XTENSA_OP_EXIT_TB_0 | + XTENSA_OP_CHECK_INTERRUPTS, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.itlbcfg", @@ -5251,7 +5276,10 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){PS}, - .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, + .op_flags =3D + XTENSA_OP_PRIVILEGED | + XTENSA_OP_EXIT_TB_M1 | + XTENSA_OP_CHECK_INTERRUPTS, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.ptevaddr", --=20 2.11.0