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X-Received-From: 2a00:1450:4864:20::144 Subject: [Qemu-devel] [PATCH 13/15] target/xtensa: extract unconditional TB termination via slot 0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" - mark instructions that require TB termination via slot 0; - put TB termination right after the instruction translation loop, if termination w/o TB linking wasn't requested; Signed-off-by: Max Filippov --- target/xtensa/translate.c | 83 ++++++++++++++++++++-----------------------= ---- 1 file changed, 36 insertions(+), 47 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 028b4d4c8652..77ee3162b2a3 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -540,14 +540,12 @@ static bool gen_rsr(DisasContext *dc, TCGv_i32 d, uin= t32_t sr) static bool gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s) { gen_helper_wsr_lbeg(cpu_env, s); - gen_jumpi_check_loop_end(dc, 0); return false; } =20 static bool gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s) { gen_helper_wsr_lend(cpu_env, s); - gen_jumpi_check_loop_end(dc, 0); return false; } =20 @@ -614,7 +612,6 @@ static bool gen_wsr_tlbcfg(DisasContext *dc, uint32_t s= r, TCGv_i32 v) static bool gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) { gen_helper_wsr_ibreakenable(cpu_env, v); - gen_jumpi_check_loop_end(dc, 0); return true; } =20 @@ -638,7 +635,6 @@ static bool gen_wsr_ibreaka(DisasContext *dc, uint32_t = sr, TCGv_i32 v) assert(id < dc->config->nibreak); gen_helper_wsr_ibreaka(cpu_env, tmp, v); tcg_temp_free(tmp); - gen_jumpi_check_loop_end(dc, 0); return true; } =20 @@ -686,7 +682,6 @@ static bool gen_wsr_intset(DisasContext *dc, uint32_t s= r, TCGv_i32 v) tcg_gen_andi_i32(cpu_SR[sr], v, dc->config->inttype_mask[INTTYPE_SOFTWARE]); gen_check_interrupts(dc); - gen_jumpi_check_loop_end(dc, 0); return true; } =20 @@ -701,7 +696,6 @@ static bool gen_wsr_intclear(DisasContext *dc, uint32_t= sr, TCGv_i32 v) tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp); tcg_temp_free(tmp); gen_check_interrupts(dc); - gen_jumpi_check_loop_end(dc, 0); return true; } =20 @@ -709,7 +703,6 @@ static bool gen_wsr_intenable(DisasContext *dc, uint32_= t sr, TCGv_i32 v) { tcg_gen_mov_i32(cpu_SR[sr], v); gen_check_interrupts(dc); - gen_jumpi_check_loop_end(dc, 0); return true; } =20 @@ -735,7 +728,6 @@ static bool gen_wsr_ccount(DisasContext *dc, uint32_t s= r, TCGv_i32 v) if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_end(); } - gen_jumpi_check_loop_end(dc, 0); return true; } =20 @@ -772,7 +764,6 @@ static bool gen_wsr_ccompare(DisasContext *dc, uint32_t= sr, TCGv_i32 v) if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_end(); } - gen_jumpi_check_loop_end(dc, 0); return true; } #else @@ -878,7 +869,6 @@ static void gen_waiti(DisasContext *dc, uint32_t imm4) } tcg_temp_free(pc); tcg_temp_free(intlevel); - gen_jumpi_check_loop_end(dc, 0); } #endif =20 @@ -1096,6 +1086,8 @@ static void disas_xtensa_insn(CPUXtensaState *env, Di= sasContext *dc) if (op_flags & XTENSA_OP_EXIT_TB_M1) { /* Change in mmu index, memory mapping or tb->flags; exit tb */ gen_jumpi_check_loop_end(dc, -1); + } else if (op_flags & XTENSA_OP_EXIT_TB_0) { + gen_jumpi_check_loop_end(dc, 0); } } =20 @@ -2152,7 +2144,6 @@ static void translate_rsil(DisasContext *dc, const ui= nt32_t arg[], tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1]); gen_check_interrupts(dc); - gen_jumpi_check_loop_end(dc, 0); } =20 static bool test_ill_rsr(DisasContext *dc, const uint32_t arg[], @@ -2164,9 +2155,7 @@ static bool test_ill_rsr(DisasContext *dc, const uint= 32_t arg[], static void translate_rsr(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - if (gen_rsr(dc, cpu_R[arg[0]], par[0])) { - gen_jumpi_check_loop_end(dc, 0); - } + gen_rsr(dc, cpu_R[arg[0]], par[0]); } =20 static void translate_rtlb(DisasContext *dc, const uint32_t arg[], @@ -2501,15 +2490,11 @@ static void translate_xsr(DisasContext *dc, const u= int32_t arg[], const uint32_t par[]) { TCGv_i32 tmp =3D tcg_temp_new_i32(); - bool rsr_end, wsr_end; =20 tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); - rsr_end =3D gen_rsr(dc, cpu_R[arg[0]], par[0]); - wsr_end =3D gen_wsr(dc, par[0], tmp); + gen_rsr(dc, cpu_R[arg[0]], par[0]); + gen_wsr(dc, par[0], tmp); tcg_temp_free(tmp); - if (rsr_end && !wsr_end) { - gen_jumpi_check_loop_end(dc, 0); - } } =20 static const XtensaOpcodeOps core_ops[] =3D { @@ -3543,7 +3528,7 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "rsil", .translate =3D translate_rsil, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "rsr.176", @@ -3617,7 +3602,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){CCOUNT}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "rsr.configid0", @@ -3904,14 +3889,14 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){INTSET}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "rsr.intset", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){INTSET}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "rsr.itlbcfg", @@ -4242,7 +4227,7 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "waiti", .translate =3D translate_waiti, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, }, { .name =3D "wdtlb", .translate =3D translate_wtlb, @@ -4315,28 +4300,28 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CCOMPARE}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.ccompare1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CCOMPARE + 1}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.ccompare2", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CCOMPARE + 2}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.ccount", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CCOUNT}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.configid0", @@ -4574,21 +4559,21 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){IBREAKA}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.ibreaka1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){IBREAKA + 1}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.ibreakenable", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){IBREAKENABLE}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.icount", @@ -4609,28 +4594,28 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){INTCLEAR}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.intenable", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){INTENABLE}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.interrupt", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){INTSET}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.intset", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){INTSET}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.itlbcfg", @@ -4644,6 +4629,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){LBEG}, + .op_flags =3D XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.lcount", @@ -4656,6 +4642,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){LEND}, + .op_flags =3D XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.litbase", @@ -4872,28 +4859,28 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CCOMPARE}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.ccompare1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CCOMPARE + 1}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.ccompare2", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CCOMPARE + 2}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.ccount", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CCOUNT}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.configid0", @@ -5131,21 +5118,21 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){IBREAKA}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.ibreaka1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){IBREAKA + 1}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.ibreakenable", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){IBREAKENABLE}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.icount", @@ -5166,28 +5153,28 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){INTCLEAR}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.intenable", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){INTENABLE}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.interrupt", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){INTSET}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.intset", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){INTSET}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.itlbcfg", @@ -5201,6 +5188,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){LBEG}, + .op_flags =3D XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.lcount", @@ -5213,6 +5201,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){LEND}, + .op_flags =3D XTENSA_OP_EXIT_TB_0, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.litbase", --=20 2.11.0