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X-Received-From: 2a00:1450:4864:20::230 Subject: [Qemu-devel] [PATCH 10/15] target/xtensa: extract unconditional TB termination X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" - mark all instructions that exit TB and require dynamic search for the next TB; - put TB termination right after the instruction translation loop; Signed-off-by: Max Filippov --- target/xtensa/translate.c | 67 ++++++++++++++++++++-----------------------= ---- 1 file changed, 28 insertions(+), 39 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index f8b9f65f7102..93289fd37f1f 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -572,8 +572,6 @@ static bool gen_wsr_br(DisasContext *dc, uint32_t sr, T= CGv_i32 s) static bool gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s) { tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001); - /* This can change tb->flags, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); return true; } =20 @@ -587,16 +585,12 @@ static bool gen_wsr_acchi(DisasContext *dc, uint32_t = sr, TCGv_i32 s) static bool gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v) { gen_helper_wsr_windowbase(cpu_env, v); - /* This can change tb->flags, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); return true; } =20 static bool gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v) { tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1); - /* This can change tb->flags, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); return true; } =20 @@ -609,8 +603,6 @@ static bool gen_wsr_ptevaddr(DisasContext *dc, uint32_t= sr, TCGv_i32 v) static bool gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v) { gen_helper_wsr_rasid(cpu_env, v); - /* This can change tb->flags, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); return true; } =20 @@ -680,8 +672,6 @@ static bool gen_wsr_dbreakc(DisasContext *dc, uint32_t = sr, TCGv_i32 v) static bool gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) { tcg_gen_andi_i32(cpu_SR[sr], v, 0xff); - /* This can change tb->flags, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); return true; } =20 @@ -738,8 +728,6 @@ static bool gen_wsr_ps(DisasContext *dc, uint32_t sr, T= CGv_i32 v) } tcg_gen_andi_i32(cpu_SR[sr], v, mask); gen_check_interrupts(dc); - /* This can change mmu index and tb->flags, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); return true; } =20 @@ -770,8 +758,6 @@ static bool gen_wsr_icount(DisasContext *dc, uint32_t s= r, TCGv_i32 v) static bool gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v) { tcg_gen_andi_i32(cpu_SR[sr], v, 0xf); - /* This can change tb->flags, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); return true; } =20 @@ -1115,6 +1101,14 @@ static void disas_xtensa_insn(CPUXtensaState *env, D= isasContext *dc) dc->raw_arg =3D slot_prop[slot].raw_arg; ops->translate(dc, slot_prop[slot].arg, ops->par); } + + if (dc->base.is_jmp =3D=3D DISAS_NEXT) { + if (op_flags & XTENSA_OP_EXIT_TB_M1) { + /* Change in mmu index, memory mapping or tb->flags; exit tb */ + gen_jumpi_check_loop_end(dc, -1); + } + } + if (dc->base.is_jmp =3D=3D DISAS_NEXT) { gen_check_loop_end(dc, 0); } @@ -1664,8 +1658,6 @@ static void translate_entry(DisasContext *dc, const u= int32_t arg[], tcg_temp_free(imm); tcg_temp_free(s); tcg_temp_free(pc); - /* This can change tb->flags, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); } =20 static void translate_extui(DisasContext *dc, const uint32_t arg[], @@ -1699,8 +1691,6 @@ static void translate_itlb(DisasContext *dc, const ui= nt32_t arg[], TCGv_i32 dtlb =3D tcg_const_i32(par[0]); =20 gen_helper_itlb(cpu_env, cpu_R[arg[0]], dtlb); - /* This could change memory mapping, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); tcg_temp_free(dtlb); #endif } @@ -2163,8 +2153,6 @@ static void translate_rotw(DisasContext *dc, const ui= nt32_t arg[], TCGv_i32 tmp =3D tcg_const_i32(arg[0]); gen_helper_rotw(cpu_env, tmp); tcg_temp_free(tmp); - /* This can change tb->flags, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); } =20 static void translate_rsil(DisasContext *dc, const uint32_t arg[], @@ -2468,8 +2456,6 @@ static void translate_wtlb(DisasContext *dc, const ui= nt32_t arg[], TCGv_i32 dtlb =3D tcg_const_i32(par[0]); =20 gen_helper_wtlb(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]], dtlb); - /* This could change memory mapping, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); tcg_temp_free(dtlb); #endif } @@ -2874,6 +2860,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_entry, .test_ill =3D test_ill_entry, .test_overflow =3D test_overflow_entry, + .op_flags =3D XTENSA_OP_EXIT_TB_M1, }, { .name =3D "esync", .translate =3D translate_nop, @@ -2897,7 +2884,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "idtlb", .translate =3D translate_itlb, .par =3D (const uint32_t[]){true}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, .windowed_register_op =3D 0x1, }, { .name =3D "ihi", @@ -2917,7 +2904,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "iitlb", .translate =3D translate_itlb, .par =3D (const uint32_t[]){false}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, .windowed_register_op =3D 0x1, }, { .name =3D "iiu", @@ -3562,7 +3549,7 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "rotw", .translate =3D translate_rotw, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, }, { .name =3D "rsil", .translate =3D translate_rsil, @@ -4270,7 +4257,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "wdtlb", .translate =3D translate_wtlb, .par =3D (const uint32_t[]){true}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, .windowed_register_op =3D 0x3, }, { .name =3D "wer", @@ -4281,7 +4268,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "witlb", .translate =3D translate_wtlb, .par =3D (const uint32_t[]){false}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, .windowed_register_op =3D 0x3, }, { .name =3D "wrmsk_expstate", @@ -4380,7 +4367,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CPENABLE}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.dbreaka0", @@ -4625,7 +4612,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){ICOUNTLEVEL}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.intclear", @@ -4685,6 +4672,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){LITBASE}, + .op_flags =3D XTENSA_OP_EXIT_TB_M1, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.m0", @@ -4764,7 +4752,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){PS}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.ptevaddr", @@ -4778,7 +4766,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){RASID}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.sar", @@ -4804,14 +4792,14 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){WINDOW_BASE}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, .windowed_register_op =3D 0x1, }, { .name =3D "wsr.windowstart", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){WINDOW_START}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, .windowed_register_op =3D 0x1, }, { .name =3D "wur.expstate", @@ -4936,7 +4924,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CPENABLE}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.dbreaka0", @@ -5181,7 +5169,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){ICOUNTLEVEL}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.intclear", @@ -5241,6 +5229,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){LITBASE}, + .op_flags =3D XTENSA_OP_EXIT_TB_M1, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.m0", @@ -5313,7 +5302,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){PS}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.ptevaddr", @@ -5327,7 +5316,7 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){RASID}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.sar", @@ -5353,14 +5342,14 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){WINDOW_BASE}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, .windowed_register_op =3D 0x1, }, { .name =3D "xsr.windowstart", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){WINDOW_START}, - .op_flags =3D XTENSA_OP_PRIVILEGED, + .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, .windowed_register_op =3D 0x1, }, }; --=20 2.11.0