From nobody Wed Nov 5 18:37:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535812481156467.96897600254067; Sat, 1 Sep 2018 07:34:41 -0700 (PDT) Received: from localhost ([::1]:37389 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fw6z2-0008Er-1P for importer@patchew.org; Sat, 01 Sep 2018 10:34:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55115) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fw6qH-0006KD-Ij for qemu-devel@nongnu.org; Sat, 01 Sep 2018 10:25:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fw6os-0005o7-5s for qemu-devel@nongnu.org; Sat, 01 Sep 2018 10:24:11 -0400 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:42842 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fw6oq-0005mx-V9; Sat, 01 Sep 2018 10:24:09 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 8627E4021715; Sat, 1 Sep 2018 14:24:08 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-157.ams2.redhat.com [10.36.116.157]) by smtp.corp.redhat.com (Postfix) with ESMTP id AC2102166B41; Sat, 1 Sep 2018 14:24:06 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org Date: Sat, 1 Sep 2018 16:23:05 +0200 Message-Id: <20180901142312.11662-14-eric.auger@redhat.com> In-Reply-To: <20180901142312.11662-1-eric.auger@redhat.com> References: <20180901142312.11662-1-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.6 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Sat, 01 Sep 2018 14:24:08 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Sat, 01 Sep 2018 14:24:08 +0000 (UTC) for IP:'10.11.54.6' DOMAIN:'int-mx06.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'eric.auger@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [RFC 13/20] hw/arm/smmuv3: Notify on config changes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yi.l.liu@intel.com, cdall@kernel.org, mst@redhat.com, jean-philippe.brucker@arm.com, peterx@redhat.com, alex.williamson@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In case IOMMU config notifiers are attached to the IOMMU memory region, we execute them, passing as argument the iommu_guest_stage_config struct updated with the new viommu translation config. Config notifiers are called on STE and CD changes. At physical level, they translate into CMD_CFGI_STE_* and CMD_CFGI_CD_* commands. Signed-off-by: Eric Auger --- hw/arm/smmuv3.c | 71 ++++++++++++++++++++++++++++++++----------------- 1 file changed, 46 insertions(+), 25 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index ff92f802bd..a31df03d47 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -16,6 +16,8 @@ * with this program; if not, see . */ =20 +#include "linux/iommu.h" + #include "qemu/osdep.h" #include "hw/boards.h" #include "sysemu/sysemu.h" @@ -843,6 +845,47 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, in= t asid, dma_addr_t iova) } } =20 +static void smmuv3_notify_config_change(SMMUState *bs, uint32_t sid) +{ + IOMMUMemoryRegion *mr =3D smmu_iommu_mr(bs, sid); + SMMUEventInfo event =3D {.type =3D SMMU_EVT_NONE, .sid =3D sid}; + SMMUTransCfg *cfg; + SMMUDevice *sdev; + + if (!mr) { + return; + } + + sdev =3D container_of(mr, SMMUDevice, iommu); + + /* flush QEMU config cache */ + smmuv3_flush_config(sdev); + + if (mr->iommu_notify_flags & IOMMU_NOTIFIER_S1_CFG) { + /* force a guest RAM config structure decoding */ + cfg =3D smmuv3_get_config(sdev, &event); + + if (cfg) { + struct iommu_guest_stage_config *kcfg =3D + g_new0(struct iommu_guest_stage_config, 1); + + kcfg->flags =3D SMMUV3_S1_CFG; + kcfg->smmu_s1.flags =3D cfg->disabled ? IOMMU_SMMU_S1_DISABLED= : 0 | + cfg->bypassed ? IOMMU_SMMU_S1_BYPASSED := 0 | + cfg->aborted ? IOMMU_SMMU_S1_ABORTED : = 0; + kcfg->smmu_s1.cdptr_dma =3D cfg->s1ctxptr; + kcfg->smmu_s1.asid_bits =3D 16; + + memory_region_config_notify_iommu(mr, 0, kcfg); + g_free(kcfg); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s error decoding the configuration for iommu m= r=3D%s\n", + __func__, mr->parent_obj.name); + } + } +} + static int smmuv3_cmdq_consume(SMMUv3State *s) { SMMUState *bs =3D ARM_SMMU(s); @@ -893,22 +936,14 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) case SMMU_CMD_CFGI_STE: { uint32_t sid =3D CMD_SID(&cmd); - IOMMUMemoryRegion *mr =3D smmu_iommu_mr(bs, sid); - SMMUDevice *sdev; =20 if (CMD_SSEC(&cmd)) { cmd_error =3D SMMU_CERROR_ILL; break; } =20 - if (!mr) { - break; - } - trace_smmuv3_cmdq_cfgi_ste(sid); - sdev =3D container_of(mr, SMMUDevice, iommu); - smmuv3_flush_config(sdev); - + smmuv3_notify_config_change(bs, sid); break; } case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */ @@ -925,14 +960,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) trace_smmuv3_cmdq_cfgi_ste_range(start, end); =20 for (i =3D start; i <=3D end; i++) { - IOMMUMemoryRegion *mr =3D smmu_iommu_mr(bs, i); - SMMUDevice *sdev; - - if (!mr) { - continue; - } - sdev =3D container_of(mr, SMMUDevice, iommu); - smmuv3_flush_config(sdev); + smmuv3_notify_config_change(bs, i); } break; } @@ -940,21 +968,14 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) case SMMU_CMD_CFGI_CD_ALL: { uint32_t sid =3D CMD_SID(&cmd); - IOMMUMemoryRegion *mr =3D smmu_iommu_mr(bs, sid); - SMMUDevice *sdev; =20 if (CMD_SSEC(&cmd)) { cmd_error =3D SMMU_CERROR_ILL; break; } =20 - if (!mr) { - break; - } - trace_smmuv3_cmdq_cfgi_cd(sid); - sdev =3D container_of(mr, SMMUDevice, iommu); - smmuv3_flush_config(sdev); + smmuv3_notify_config_change(bs, sid); break; } case SMMU_CMD_TLBI_NH_ASID: --=20 2.17.1