From nobody Wed Nov 5 16:36:57 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535714837130671.7653757878784; Fri, 31 Aug 2018 04:27:17 -0700 (PDT) Received: from localhost ([::1]:53105 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvha8-0008Mk-7B for importer@patchew.org; Fri, 31 Aug 2018 07:27:16 -0400 Received: from eggs.gnu.org ([208.118.235.92]:37245) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvhVt-0004PW-Iq for qemu-devel@nongnu.org; Fri, 31 Aug 2018 07:22:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fvhPP-0004cF-QI for qemu-devel@nongnu.org; Fri, 31 Aug 2018 07:16:15 -0400 Received: from 16.mo1.mail-out.ovh.net ([178.33.104.224]:44330) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fvhPP-0004bn-Ix for qemu-devel@nongnu.org; Fri, 31 Aug 2018 07:16:11 -0400 Received: from player714.ha.ovh.net (unknown [10.109.146.137]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id 190E4126DE1 for ; Fri, 31 Aug 2018 13:16:09 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player714.ha.ovh.net (Postfix) with ESMTPSA id 796F23C00C7; Fri, 31 Aug 2018 13:16:00 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Date: Fri, 31 Aug 2018 13:15:54 +0200 Message-Id: <20180831111555.15008-1-clg@kaod.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180831103816.13479-1-clg@kaod.org> References: <20180831103816.13479-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2556074264368876352 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtjedrhedtgdeflecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.33.104.224 Subject: [Qemu-devel] [PATCH 10/11] aspeed/smc: inject errors in DMA checksum X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Andrew Jeffery , Alistair Francis , qemu-arm@nongnu.org, Joel Stanley , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Emulate read errors in the DMA Checksum Register for high frequencies and optimistic settings of the Read Timing Compensation Register. This will help in tuning the SPI timing calibration algorithm. The values below are those to expect from the first flash device of the FMC controller of a palmetto-bmc machine. Signed-off-by: C=C3=A9dric Le Goater --- hw/ssi/aspeed_smc.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 983066f5ad1d..da2fedfcd3cd 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -745,6 +745,30 @@ static void aspeed_smc_dma_calibration(AspeedSMCState = *s) s->regs[s->r_ctrl0 + cs] |=3D CE_CTRL_CLOCK_FREQ(hclk_div); } =20 +static bool aspeed_smc_inject_read_failure(AspeedSMCState *s) +{ + uint8_t delay =3D + (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MAS= K; + uint8_t hclk_mask =3D + (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; + + /* + * Typical values of a palmetto-bmc machine. + */ + switch (aspeed_smc_hclk_divisor(hclk_mask)) { + case 4 ... 16: + return false; + case 3: /* at least one HCLK cycle delay */ + return (delay & 0x7) < 1; + case 2: /* at least two HCLK cycle delay */ + return (delay & 0x7) < 2; + case 1: /* (> 100MHz) is above the max freq of the controller */ + return true; + default: + g_assert_not_reached(); + } +} + /* * Accumulate the result of the reads to provide a checksum that will * be used to validate the read timing settings. @@ -774,6 +798,11 @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s) s->regs[R_DMA_FLASH_ADDR] +=3D 4; s->regs[R_DMA_LEN] -=3D 4; } + + if (aspeed_smc_inject_read_failure(s)) { + s->regs[R_DMA_CHECKSUM] =3D 0xbadc0de; + } + } =20 static void aspeed_smc_dma_rw(AspeedSMCState *s) --=20 2.17.1