From nobody Wed Nov 5 16:36:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153571236572182.22553187181927; Fri, 31 Aug 2018 03:46:05 -0700 (PDT) Received: from localhost ([::1]:52994 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvgwG-0001l3-Ly for importer@patchew.org; Fri, 31 Aug 2018 06:46:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46252) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvgpw-0003G7-65 for qemu-devel@nongnu.org; Fri, 31 Aug 2018 06:39:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fvgps-0002Em-Sr for qemu-devel@nongnu.org; Fri, 31 Aug 2018 06:39:32 -0400 Received: from 7.mo2.mail-out.ovh.net ([188.165.48.182]:40876) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fvgps-0002DZ-LD for qemu-devel@nongnu.org; Fri, 31 Aug 2018 06:39:28 -0400 Received: from player168.ha.ovh.net (unknown [10.109.159.68]) by mo2.mail-out.ovh.net (Postfix) with ESMTP id 327EB156B23 for ; Fri, 31 Aug 2018 12:39:27 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player168.ha.ovh.net (Postfix) with ESMTPSA id CD73142008C; Fri, 31 Aug 2018 12:39:18 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Date: Fri, 31 Aug 2018 12:38:14 +0200 Message-Id: <20180831103816.13479-8-clg@kaod.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180831103816.13479-1-clg@kaod.org> References: <20180831103816.13479-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 1936266368223120192 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtjedrhedtgdeftdcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 188.165.48.182 Subject: [Qemu-devel] [PATCH 07/11] aspeed/smc: add a 'sdram_base' and 'max-ram-size' properties X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Andrew Jeffery , Alistair Francis , qemu-arm@nongnu.org, Joel Stanley , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The setting of the DRAM address of the DMA transaction depends on the DRAM base address and the maximun DRAM size of the SoC. Let's add a couple of properties to give this information to the SMC controller model. Also, move the SDRAM Memory controller realization before the other controllers which need it. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ssi/aspeed_smc.h | 4 ++++ hw/arm/aspeed_soc.c | 28 +++++++++++++++++++--------- hw/ssi/aspeed_smc.c | 2 ++ 3 files changed, 25 insertions(+), 9 deletions(-) diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index 1f557313fa93..d7090bb5e9b7 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -97,6 +97,10 @@ typedef struct AspeedSMCState { uint8_t r_timings; uint8_t conf_enable_w0; =20 + /* for DMA support */ + uint64_t sdram_base; + uint64_t max_ram_size; + AspeedSMCFlash *flashes; } AspeedSMCState; =20 diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 2cbacb4430bb..bbc05d172fe1 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -209,6 +209,14 @@ static void aspeed_soc_realize(DeviceState *dev, Error= **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE); =20 + /* SDMC - SDRAM Memory Controller */ + object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE); + /* VIC */ object_property_set_bool(OBJECT(&s->vic), true, "realized", &err); if (err) { @@ -252,7 +260,17 @@ static void aspeed_soc_realize(DeviceState *dev, Error= **errp) qdev_get_gpio_in(DEVICE(&s->vic), 12)); =20 /* FMC, The number of CS is set at the board level */ - object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); + object_property_set_int(OBJECT(&s->fmc), sc->info->sdram_base, "sdram-= base", + &err); + object_property_set_int(OBJECT(&s->fmc), s->sdmc.max_ram_size, + "max-ram-size", &local_err); + error_propagate(&err, local_err); + if (err) { + error_propagate(errp, err); + return; + } + object_property_set_bool(OBJECT(&s->fmc), true, "realized", &local_err= ); + error_propagate(&err, local_err); if (err) { error_propagate(errp, err); return; @@ -278,14 +296,6 @@ static void aspeed_soc_realize(DeviceState *dev, Error= **errp) s->spi[i].ctrl->flash_window_base); } =20 - /* SDMC - SDRAM Memory Controller */ - object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE); - /* Watch dog */ for (i =3D 0; i < sc->info->wdts_num; i++) { object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &er= r); diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 6045ca11b969..500de6d16d09 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -800,6 +800,8 @@ static const VMStateDescription vmstate_aspeed_smc =3D { =20 static Property aspeed_smc_properties[] =3D { DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1), + DEFINE_PROP_UINT64("sdram-base", AspeedSMCState, sdram_base, 0), + DEFINE_PROP_UINT64("max-ram-size", AspeedSMCState, max_ram_size, 0), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.17.1