From nobody Wed Nov 5 16:38:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@amazon.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535658674962891.8343038236746; Thu, 30 Aug 2018 12:51:14 -0700 (PDT) Received: from localhost ([::1]:50616 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvSyH-0006sv-QE for importer@patchew.org; Thu, 30 Aug 2018 15:51:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49333) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvSt3-0001J9-I9 for qemu-devel@nongnu.org; Thu, 30 Aug 2018 15:45:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fvSeE-0006pr-1T for qemu-devel@nongnu.org; Thu, 30 Aug 2018 15:30:33 -0400 Received: from smtp-fw-6002.amazon.com ([52.95.49.90]:40690) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1fvSeD-0006pC-QT for qemu-devel@nongnu.org; Thu, 30 Aug 2018 15:30:29 -0400 Received: from iad6-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-2a-6e2fc477.us-west-2.amazon.com) ([10.124.125.6]) by smtp-border-fw-out-6002.iad6.amazon.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 30 Aug 2018 19:30:28 +0000 Received: from ua08cfde8192f59f8a244.ant.amazon.com (pdx2-ws-svc-lb17-vlan3.amazon.com [10.247.140.70]) by email-inbound-relay-2a-6e2fc477.us-west-2.amazon.com (8.14.7/8.14.7) with ESMTP id w7UJUPEO012203 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 30 Aug 2018 19:30:25 GMT Received: from ua08cfde8192f59f8a244.ant.amazon.com (localhost [127.0.0.1]) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id w7UJUP4B020242; Thu, 30 Aug 2018 15:30:25 -0400 Received: (from jancraig@localhost) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Submit) id w7UJUPbp020241; Thu, 30 Aug 2018 15:30:25 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1535657429; x=1567193429; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=TvRxK6KOOtspkJw0ObkMOnXstkFOjWXC4TEVQGG55go=; b=VgOiK54caUAY2wPKJrZHvnXtsqANWobCCp95nQBpUlJh5DgxQ9Yik05U Ro8LPd0q2u+ZCoYxamCbmeAy+SeuIljeB6sN/5I63iStdsTh7JCmdKQmG 2NCm3KqcJcum/uYDy1rhvtYiYIGZJmd796fmezPHkAx0yCyOAq2+AOwF4 E=; X-IronPort-AV: E=Sophos;i="5.53,307,1531785600"; d="scan'208";a="359978313" To: qemu-devel@nongnu.org Date: Thu, 30 Aug 2018 15:30:16 -0400 Message-Id: <20180830193019.20104-7-jancraig@amazon.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180830193019.20104-1-jancraig@amazon.com> References: <20180830193019.20104-1-jancraig@amazon.com> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 52.95.49.90 Subject: [Qemu-devel] [PATCH v4 6/9] target/mips: Add MXU instruction D16MUL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds support for emulating the D16MUL instruction. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - changed bitfield usage to extract32 - used sextract_tl instructions instead of shift and ext v3 - Split gen_mxu function into command specific gen_mxu_ functions v4 - Add and use MXU_OPTN2_ #defines - Add check for MXUEN target/mips/translate.c | 70 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index cfd25c3abe..0241f1fca4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -3849,6 +3849,12 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, #define MXU_OPTN3_PTN6 6 #define MXU_OPTN3_PTN7 7 =20 +/* MXU operand getting patterns */ +#define MXU_OPTN2_WW 0 +#define MXU_OPTN2_LW 1 +#define MXU_OPTN2_HW 2 +#define MXU_OPTN2_XW 3 + /* S32I2M XRa, rb - Register move from GRF to XRF */ static void gen_mxu_s32i2m(DisasContext *ctx, uint32_t opc) { @@ -3974,6 +3980,66 @@ static void gen_mxu_s8ldd(DisasContext *ctx, uint32_= t opc) tcg_temp_free(t1); } =20 +/* D16MUL XRa, XRb, XRc, XRd, OPTN2 - Signed 16 bit pattern multiplication= */ +static void gen_mxu_d16mul(DisasContext *ctx, uint32_t opc) +{ + TCGv t0, t1, t2, t3; + TCGLabel *l0; + uint32_t xra, xrb, xrc, xrd, optn2; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + t2 =3D tcg_temp_new(); + t3 =3D tcg_temp_new(); + + l0 =3D gen_new_label(); + + xra =3D extract32(ctx->opcode, 6, 4); + xrb =3D extract32(ctx->opcode, 10, 4); + xrc =3D extract32(ctx->opcode, 14, 4); + xrd =3D extract32(ctx->opcode, 18, 4); + optn2 =3D extract32(ctx->opcode, 22, 2); + + gen_load_mxu_cr(t0); + tcg_gen_andi_tl(t0, t0, MXUEN); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXUEN, l0); + + gen_load_mxu_gpr(t1, xrb); + tcg_gen_sextract_tl(t0, t1, 0, 16); + tcg_gen_sextract_tl(t1, t1, 16, 16); + gen_load_mxu_gpr(t3, xrc); + tcg_gen_sextract_tl(t2, t3, 0, 16); + tcg_gen_sextract_tl(t3, t3, 16, 16); + + switch (optn2) { + case MXU_OPTN2_WW: /* XRB.H*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case MXU_OPTN2_LW: /* XRB.L*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case MXU_OPTN2_HW: /* XRB.H*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + case MXU_OPTN2_XW: /* XRB.L*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + } + gen_store_mxu_gpr(t3, xra); + gen_store_mxu_gpr(t2, xrd); + + gen_set_label(l0); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); +} + /* Godson integer instructions */ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) @@ -18050,6 +18116,10 @@ static void decode_opc_special2_mxu(CPUMIPSState *= env, DisasContext *ctx) gen_mxu_s8ldd(ctx, op1); break; =20 + case OPC_MXU_D16MUL: + gen_mxu_d16mul(ctx, op1); + break; + default: /* Invalid */ MIPS_INVAL("special2_mxu"); generate_exception_end(ctx, EXCP_RI); --=20 2.18.0