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X-Received-From: 207.171.190.10 Subject: [Qemu-devel] [PATCH v4 2/9] target/mips: Add all MXU opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds all MXU opcodes to the opcode enum. Signed-off-by: Craig Janeczek --- v1 - NA v2 - NA v3 - Initial patch, split out from prior first patch v4 - separate MXU opcodes into their own enum target/mips/translate.c | 60 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 19b90c8735..a598f45558 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -368,6 +368,66 @@ enum { OPC_SDBBP =3D 0x3F | OPC_SPECIAL2, }; =20 +enum { + /* MXU */ + OPC_MXU_S32MADD =3D 0x00 | OPC_SPECIAL2, + OPC_MXU_S32MADDU =3D 0x01 | OPC_SPECIAL2, + OPC_MXU_D16MAX =3D 0x03 | OPC_SPECIAL2, + OPC_MXU_S32MSUB =3D 0x04 | OPC_SPECIAL2, + OPC_MXU_S32MSUBU =3D 0x05 | OPC_SPECIAL2, + OPC_MXU_D16AVG =3D 0x06 | OPC_SPECIAL2, + OPC_MXU_D16CPS =3D 0x07 | OPC_SPECIAL2, + OPC_MXU_D16MUL =3D 0x08 | OPC_SPECIAL2, + OPC_MXU_D16MULF =3D 0x09 | OPC_SPECIAL2, + OPC_MXU_D16MAC =3D 0x0A | OPC_SPECIAL2, + OPC_MXU_D16MACF =3D 0x0B | OPC_SPECIAL2, + OPC_MXU_D16MADL =3D 0x0C | OPC_SPECIAL2, + OPC_MXU_S16MAD =3D 0x0D | OPC_SPECIAL2, + OPC_MXU_Q16ADD =3D 0x0E | OPC_SPECIAL2, + OPC_MXU_D16MACE =3D 0x0F | OPC_SPECIAL2, + OPC_MXU_S32LDD =3D 0x10 | OPC_SPECIAL2, + OPC_MXU_S32STD =3D 0x11 | OPC_SPECIAL2, + OPC_MXU_S32LDDV =3D 0x12 | OPC_SPECIAL2, + OPC_MXU_S32STDV =3D 0x13 | OPC_SPECIAL2, + OPC_MXU_S32LDI =3D 0x14 | OPC_SPECIAL2, + OPC_MXU_S32SDI =3D 0x15 | OPC_SPECIAL2, + OPC_MXU_S32LDIV =3D 0x16 | OPC_SPECIAL2, + OPC_MXU_S32SDIV =3D 0x17 | OPC_SPECIAL2, + OPC_MXU_D32ADD =3D 0x18 | OPC_SPECIAL2, + OPC_MXU_D32ACC =3D 0x19 | OPC_SPECIAL2, + OPC_MXU_Q16ACC =3D 0x1B | OPC_SPECIAL2, + OPC_MXU_Q8ADDE =3D 0x1C | OPC_SPECIAL2, + OPC_MXU_Q8ACCE =3D 0x1D | OPC_SPECIAL2, + OPC_MXU_S8LDD =3D 0x22 | OPC_SPECIAL2, + OPC_MXU_S8STD =3D 0x23 | OPC_SPECIAL2, + OPC_MXU_S8LDI =3D 0x24 | OPC_SPECIAL2, + OPC_MXU_S8SDI =3D 0x25 | OPC_SPECIAL2, + OPC_MXU_S32EXTR =3D 0x26 | OPC_SPECIAL2, + OPC_MXU_D32SARW =3D 0x27 | OPC_SPECIAL2, + OPC_MXU_LXB =3D 0x28 | OPC_SPECIAL2, + OPC_MXU_S16LDD =3D 0x2A | OPC_SPECIAL2, + OPC_MXU_S16STD =3D 0x2B | OPC_SPECIAL2, + OPC_MXU_S16LDI =3D 0x2C | OPC_SPECIAL2, + OPC_MXU_S16SDI =3D 0x2D | OPC_SPECIAL2, + OPC_MXU_S32M2I =3D 0x2E | OPC_SPECIAL2, + OPC_MXU_S32I2M =3D 0x2F | OPC_SPECIAL2, + OPC_MXU_D32SLL =3D 0x30 | OPC_SPECIAL2, + OPC_MXU_D32SLR =3D 0x31 | OPC_SPECIAL2, + OPC_MXU_D32SARL =3D 0x32 | OPC_SPECIAL2, + OPC_MXU_D32SAR =3D 0x33 | OPC_SPECIAL2, + OPC_MXU_Q16SLL =3D 0x34 | OPC_SPECIAL2, + OPC_MXU_Q16SLR =3D 0x35 | OPC_SPECIAL2, + OPC_MXU_D32SLLV =3D 0x36 | OPC_SPECIAL2, + OPC_MXU_Q16SAR =3D 0x37 | OPC_SPECIAL2, + OPC_MXU_Q8MUL =3D 0x38 | OPC_SPECIAL2, + OPC_MXU_Q8MOVZ =3D 0x39 | OPC_SPECIAL2, + OPC_MXU_Q8MAC =3D 0x3A | OPC_SPECIAL2, + OPC_MXU_Q16SCOP =3D 0x3B | OPC_SPECIAL2, + OPC_MXU_Q8MADL =3D 0x3C | OPC_SPECIAL2, + OPC_MXU_S32SFL =3D 0x3D | OPC_SPECIAL2, + OPC_MXU_Q8SAD =3D 0x3E | OPC_SPECIAL2, +}; + /* Special3 opcodes */ #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F) =20 --=20 2.18.0