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X-Received-From: 207.171.184.25 Subject: [Qemu-devel] [PATCH v4 9/9] target/mips: Add MXU instructions S32LDD and S32LDDR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds support for emulating the S32LDD and S32LDDR MXU instructions. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - changed bitfield usage to extract32 v3 - Split gen_mxu function into command specific gen_mxu_ functions v4 - Add check for MXUEN target/mips/translate.c | 49 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 31c7342261..297f913d36 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4222,6 +4222,51 @@ static void gen_mxu_q8mul(DisasContext *ctx, uint32_= t opc) tcg_temp_free(t7); } =20 +/* S32LDD XRa, rb, S12 - Load a word from memory to XRF + * S32LDDR XRa, rb, S12 - Load a word from memory to XRF, + * reversed byte sequence */ +static void gen_mxu_s32ldd(DisasContext *ctx, uint32_t opc) +{ + TCGv t0, t1; + TCGLabel *l0; + uint32_t xra, s12, sel, rb; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + + l0 =3D gen_new_label(); + + xra =3D extract32(ctx->opcode, 6, 4); + s12 =3D extract32(ctx->opcode, 10, 10); + sel =3D extract32(ctx->opcode, 20, 1); + rb =3D extract32(ctx->opcode, 21, 5); + + gen_load_mxu_cr(t0); + tcg_gen_andi_tl(t0, t0, MXUEN); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXUEN, l0); + + gen_load_gpr(t0, rb); + + tcg_gen_movi_tl(t1, s12); + tcg_gen_shli_tl(t1, t1, 2); + if (s12 & 0x200) { + tcg_gen_ori_tl(t1, t1, 0xFFFFF000); + } + tcg_gen_add_tl(t1, t0, t1); + tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_SL); + + if (sel =3D=3D 1) { + /* S32LDDR */ + tcg_gen_bswap32_tl(t1, t1); + } + gen_store_mxu_gpr(t1, xra); + + gen_set_label(l0); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} + /* Godson integer instructions */ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) @@ -18310,6 +18355,10 @@ static void decode_opc_special2_mxu(CPUMIPSState *= env, DisasContext *ctx) gen_mxu_q8mul(ctx, op1); break; =20 + case OPC_MXU_S32LDD: + gen_mxu_s32ldd(ctx, op1); + break; + default: /* Invalid */ MIPS_INVAL("special2_mxu"); generate_exception_end(ctx, EXCP_RI); --=20 2.18.0