From nobody Sat Feb 7 02:58:18 2026 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@amazon.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535658889230851.2980580156099; Thu, 30 Aug 2018 12:54:49 -0700 (PDT) Received: from localhost ([::1]:50634 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvT1k-00030M-4x for importer@patchew.org; Thu, 30 Aug 2018 15:54:48 -0400 Received: from eggs.gnu.org ([208.118.235.92]:59985) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvSsz-000139-AQ for qemu-devel@nongnu.org; Thu, 30 Aug 2018 15:45:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fvSfR-0007QF-2n for qemu-devel@nongnu.org; Thu, 30 Aug 2018 15:31:49 -0400 Received: from smtp-fw-4101.amazon.com ([72.21.198.25]:40926) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1fvSfQ-0007Q7-Tt for qemu-devel@nongnu.org; Thu, 30 Aug 2018 15:31:45 -0400 Received: from iad6-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-2c-579b7f5b.us-west-2.amazon.com) ([10.124.125.6]) by smtp-border-fw-out-4101.iad4.amazon.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 30 Aug 2018 19:31:42 +0000 Received: from ua08cfde8192f59f8a244.ant.amazon.com (pdx2-ws-svc-lb17-vlan2.amazon.com [10.247.140.66]) by email-inbound-relay-2c-579b7f5b.us-west-2.amazon.com (8.14.7/8.14.7) with ESMTP id w7UJUOq8113368 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 30 Aug 2018 19:30:25 GMT Received: from ua08cfde8192f59f8a244.ant.amazon.com (localhost [127.0.0.1]) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id w7UJUOud020221; Thu, 30 Aug 2018 15:30:24 -0400 Received: (from jancraig@localhost) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Submit) id w7UJUOPp020220; Thu, 30 Aug 2018 15:30:24 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1535657504; x=1567193504; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=h0y8njRTRK/Jnj29I5qX9jo/3KJfkxzChwwuHThHPLI=; b=k4vivMRghE5z8FJPtljkD3OGMzeQvMtcBYKMdpHCtEe08O1EuSV39d1L NPvbEBdJ1SNv8Y/krS7WoMMvb2JTHKTM+GWUdaCqXwx0VmQEE4qix+b2z dJKmO7OXQH7VBwvKLE5MOOwZwbNqe6fi8EWBPvl/ppzVmY5Pzp9Ewfjyt A=; X-IronPort-AV: E=Sophos;i="5.53,307,1531785600"; d="scan'208";a="736240734" To: qemu-devel@nongnu.org Date: Thu, 30 Aug 2018 15:30:11 -0400 Message-Id: <20180830193019.20104-2-jancraig@amazon.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180830193019.20104-1-jancraig@amazon.com> References: <20180830193019.20104-1-jancraig@amazon.com> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 72.21.198.25 Subject: [Qemu-devel] [PATCH v4 1/9] target/mips: Introduce MXU registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Define and initialize the 16 MXU registers. Signed-off-by: Craig Janeczek Reviewed-by: Richard Henderson --- v1 - NA v2 - NA v3 - Initial patch, split out from prior first patch v4 - fixed reg name alignment - added braces around init for loop - Split mxu_CR out of the mxu_gpr array target/mips/cpu.h | 2 ++ target/mips/translate.c | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 009202cf64..ff356f529b 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -170,6 +170,8 @@ struct TCState { MSACSR_FS_MASK) =20 float_status msa_fp_status; + target_ulong mxu_gpr[15]; + target_ulong mxu_cr; }; =20 typedef struct CPUMIPSState CPUMIPSState; diff --git a/target/mips/translate.c b/target/mips/translate.c index bdd880bb77..19b90c8735 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1398,6 +1398,10 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31; static TCGv_i64 fpu_f64[32]; static TCGv_i64 msa_wr_d[64]; =20 +/* MXU registers */ +static TCGv mxu_gpr[15]; +static TCGv mxu_CR; + #include "exec/gen-icount.h" =20 #define gen_helper_0e0i(name, arg) do { \ @@ -1517,6 +1521,11 @@ static const char * const msaregnames[] =3D { "w30.d0", "w30.d1", "w31.d0", "w31.d1", }; =20 +static const char * const mxuregnames[] =3D { + "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8", + "XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "XR16", +}; + #define LOG_DISAS(...) = \ do { = \ if (MIPS_DEBUG_DISAS) { = \ @@ -20742,6 +20751,17 @@ void mips_tcg_init(void) fpu_fcr31 =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMIPSState, active_fpu.f= cr31), "fcr31"); + + for (i =3D 0; i < 15; i++) { + mxu_gpr[i] =3D tcg_global_mem_new(cpu_env, + offsetof(CPUMIPSState, + active_tc.mxu_gpr[i]), + mxuregnames[i]); + } + + mxu_CR =3D tcg_global_mem_new(cpu_env, + offsetof(CPUMIPSState, active_tc.mxu_cr), + "MXU_CR"); } =20 #include "translate_init.inc.c" --=20 2.18.0 From nobody Sat Feb 7 02:58:18 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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Thu, 30 Aug 2018 15:30:24 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1535657661; x=1567193661; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=cqx3X2ReJIjzj5V4/DB/6fC9PHIKW1WsJprGKz7c44I=; b=el/d27bj8PJrhE7+3fDKQuz51Jd6mplnfHmV2ke5EdNG3cJHqtSyjGom SoGJAuX3rH/4UbIdc28jelrqKpuJLlBqD1QoVmKmqjQbJZpdAlZrXR732 m0/7enUlP+A7QiGZ5VESBBl7jzLbLrvudzPSh//9D5GMRim6mydq5dGoh Y=; X-IronPort-AV: E=Sophos;i="5.53,307,1531785600"; d="scan'208";a="751298822" To: qemu-devel@nongnu.org Date: Thu, 30 Aug 2018 15:30:12 -0400 Message-Id: <20180830193019.20104-3-jancraig@amazon.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180830193019.20104-1-jancraig@amazon.com> References: <20180830193019.20104-1-jancraig@amazon.com> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 207.171.190.10 Subject: [Qemu-devel] [PATCH v4 2/9] target/mips: Add all MXU opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds all MXU opcodes to the opcode enum. Signed-off-by: Craig Janeczek --- v1 - NA v2 - NA v3 - Initial patch, split out from prior first patch v4 - separate MXU opcodes into their own enum target/mips/translate.c | 60 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 19b90c8735..a598f45558 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -368,6 +368,66 @@ enum { OPC_SDBBP =3D 0x3F | OPC_SPECIAL2, }; =20 +enum { + /* MXU */ + OPC_MXU_S32MADD =3D 0x00 | OPC_SPECIAL2, + OPC_MXU_S32MADDU =3D 0x01 | OPC_SPECIAL2, + OPC_MXU_D16MAX =3D 0x03 | OPC_SPECIAL2, + OPC_MXU_S32MSUB =3D 0x04 | OPC_SPECIAL2, + OPC_MXU_S32MSUBU =3D 0x05 | OPC_SPECIAL2, + OPC_MXU_D16AVG =3D 0x06 | OPC_SPECIAL2, + OPC_MXU_D16CPS =3D 0x07 | OPC_SPECIAL2, + OPC_MXU_D16MUL =3D 0x08 | OPC_SPECIAL2, + OPC_MXU_D16MULF =3D 0x09 | OPC_SPECIAL2, + OPC_MXU_D16MAC =3D 0x0A | OPC_SPECIAL2, + OPC_MXU_D16MACF =3D 0x0B | OPC_SPECIAL2, + OPC_MXU_D16MADL =3D 0x0C | OPC_SPECIAL2, + OPC_MXU_S16MAD =3D 0x0D | OPC_SPECIAL2, + OPC_MXU_Q16ADD =3D 0x0E | OPC_SPECIAL2, + OPC_MXU_D16MACE =3D 0x0F | OPC_SPECIAL2, + OPC_MXU_S32LDD =3D 0x10 | OPC_SPECIAL2, + OPC_MXU_S32STD =3D 0x11 | OPC_SPECIAL2, + OPC_MXU_S32LDDV =3D 0x12 | OPC_SPECIAL2, + OPC_MXU_S32STDV =3D 0x13 | OPC_SPECIAL2, + OPC_MXU_S32LDI =3D 0x14 | OPC_SPECIAL2, + OPC_MXU_S32SDI =3D 0x15 | OPC_SPECIAL2, + OPC_MXU_S32LDIV =3D 0x16 | OPC_SPECIAL2, + OPC_MXU_S32SDIV =3D 0x17 | OPC_SPECIAL2, + OPC_MXU_D32ADD =3D 0x18 | OPC_SPECIAL2, + OPC_MXU_D32ACC =3D 0x19 | OPC_SPECIAL2, + OPC_MXU_Q16ACC =3D 0x1B | OPC_SPECIAL2, + OPC_MXU_Q8ADDE =3D 0x1C | OPC_SPECIAL2, + OPC_MXU_Q8ACCE =3D 0x1D | OPC_SPECIAL2, + OPC_MXU_S8LDD =3D 0x22 | OPC_SPECIAL2, + OPC_MXU_S8STD =3D 0x23 | OPC_SPECIAL2, + OPC_MXU_S8LDI =3D 0x24 | OPC_SPECIAL2, + OPC_MXU_S8SDI =3D 0x25 | OPC_SPECIAL2, + OPC_MXU_S32EXTR =3D 0x26 | OPC_SPECIAL2, + OPC_MXU_D32SARW =3D 0x27 | OPC_SPECIAL2, + OPC_MXU_LXB =3D 0x28 | OPC_SPECIAL2, + OPC_MXU_S16LDD =3D 0x2A | OPC_SPECIAL2, + OPC_MXU_S16STD =3D 0x2B | OPC_SPECIAL2, + OPC_MXU_S16LDI =3D 0x2C | OPC_SPECIAL2, + OPC_MXU_S16SDI =3D 0x2D | OPC_SPECIAL2, + OPC_MXU_S32M2I =3D 0x2E | OPC_SPECIAL2, + OPC_MXU_S32I2M =3D 0x2F | OPC_SPECIAL2, + OPC_MXU_D32SLL =3D 0x30 | OPC_SPECIAL2, + OPC_MXU_D32SLR =3D 0x31 | OPC_SPECIAL2, + OPC_MXU_D32SARL =3D 0x32 | OPC_SPECIAL2, + OPC_MXU_D32SAR =3D 0x33 | OPC_SPECIAL2, + OPC_MXU_Q16SLL =3D 0x34 | OPC_SPECIAL2, + OPC_MXU_Q16SLR =3D 0x35 | OPC_SPECIAL2, + OPC_MXU_D32SLLV =3D 0x36 | OPC_SPECIAL2, + OPC_MXU_Q16SAR =3D 0x37 | OPC_SPECIAL2, + OPC_MXU_Q8MUL =3D 0x38 | OPC_SPECIAL2, + OPC_MXU_Q8MOVZ =3D 0x39 | OPC_SPECIAL2, + OPC_MXU_Q8MAC =3D 0x3A | OPC_SPECIAL2, + OPC_MXU_Q16SCOP =3D 0x3B | OPC_SPECIAL2, + OPC_MXU_Q8MADL =3D 0x3C | OPC_SPECIAL2, + OPC_MXU_S32SFL =3D 0x3D | OPC_SPECIAL2, + OPC_MXU_Q8SAD =3D 0x3E | OPC_SPECIAL2, +}; + /* Special3 opcodes */ #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F) =20 --=20 2.18.0 From nobody Sat Feb 7 02:58:18 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@amazon.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15356584478664.1083593070479765; Thu, 30 Aug 2018 12:47:27 -0700 (PDT) Received: from localhost ([::1]:50594 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvSuc-0002Bk-79 for importer@patchew.org; Thu, 30 Aug 2018 15:47:26 -0400 Received: from eggs.gnu.org ([208.118.235.92]:59985) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvSsf-000139-VQ for qemu-devel@nongnu.org; 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Thu, 30 Aug 2018 15:30:24 -0400 Received: (from jancraig@localhost) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Submit) id w7UJUO85020228; Thu, 30 Aug 2018 15:30:24 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1535657430; x=1567193430; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=1jHf+K1yr+uyGjqhGf03vbDWI3PRKbudYGlWB3k3shA=; b=qcZwmans/p6QD0ePk3jml9dgaJxhf6mBwf9rCdhEfRYIpphyFRWG/C0M bAx7SKwVTHWC9iR6pcRgJo0mItdnwI/zsfZG2VTm3hGoUSncg+AYixdTQ 2a3Y2KUOKbd9T1cgv4ltV6GsVV+2r5deBzJ5QL5L8axgBdoe6Np8OTqY/ k=; X-IronPort-AV: E=Sophos;i="5.53,307,1531785600"; d="scan'208";a="736240524" To: qemu-devel@nongnu.org Date: Thu, 30 Aug 2018 15:30:13 -0400 Message-Id: <20180830193019.20104-4-jancraig@amazon.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180830193019.20104-1-jancraig@amazon.com> References: <20180830193019.20104-1-jancraig@amazon.com> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 72.21.198.25 Subject: [Qemu-devel] [PATCH v4 3/9] target/mips: Split mips instruction handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Splits the instruction handling switch statement from the original legacy code. Signed-off-by: Craig Janeczek --- v1 - NA v2 - NA v3 - NA v4 - Initial patch target/mips/mips-defs.h | 1 + target/mips/translate.c | 28 +++++++++++++++++++++++++++- 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index d239069975..5a409757f0 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -50,6 +50,7 @@ #define ASE_SMARTMIPS 0x00400000 #define ASE_MICROMIPS 0x00800000 #define ASE_MSA 0x01000000 +#define ASE_MXU 0x02000000 =20 /* Chip specific instructions. */ #define INSN_LOONGSON2E 0x20000000 diff --git a/target/mips/translate.c b/target/mips/translate.c index a598f45558..53d896ebf9 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -17855,6 +17855,28 @@ static void decode_opc_special(CPUMIPSState *env, = DisasContext *ctx) } } =20 +static void decode_opc_special2_mxu(CPUMIPSState *env, DisasContext *ctx) +{ + int rs, rt, rd; + uint32_t op1; + + rs =3D (ctx->opcode >> 21) & 0x1f; + rt =3D (ctx->opcode >> 16) & 0x1f; + rd =3D (ctx->opcode >> 11) & 0x1f; + + op1 =3D MASK_SPECIAL2(ctx->opcode); + + switch (op1) { + case OPC_MUL: + gen_arith(ctx, op1, rd, rs, rt); + break; + default: /* Invalid */ + MIPS_INVAL("special2_mxu"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ct= x) { int rs, rt, rd; @@ -19836,7 +19858,11 @@ static void decode_opc(CPUMIPSState *env, DisasCon= text *ctx) decode_opc_special(env, ctx); break; case OPC_SPECIAL2: - decode_opc_special2_legacy(env, ctx); + if (ctx->insn_flags & ASE_MXU) { + decode_opc_special2_mxu(env, ctx); + } else { + decode_opc_special2_legacy(env, ctx); + } break; case OPC_SPECIAL3: decode_opc_special3(env, ctx); --=20 2.18.0 From nobody Sat Feb 7 02:58:18 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 207.171.190.10 Subject: [Qemu-devel] [PATCH v4 4/9] target/mips: Add MXU instructions S32I2M and S32M2I X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This commit makes the MXU registers and the utility functions for reading/writing to them. This is required for full MXU instruction support. Adds support for emulating the S32I2M and S32M2I MXU instructions. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - Fix checkpatch.pl errors - remove mips64 ifdef - changed bitfield usage to extract32 - squashed register addition patch into this one v3 - Split register addition and opcode enum definition into seperate patc= hes - Split gen_mxu function into command specific gen_mxu_ functions v4 - changed MXU register utility functions to take in unsigned argument - Created seperate utility functions for MXU_CR - Moved ins handling to mxu specific switch statement target/mips/translate.c | 83 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 53d896ebf9..41081ee066 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1619,6 +1619,34 @@ static inline void gen_store_gpr (TCGv t, int reg) tcg_gen_mov_tl(cpu_gpr[reg], t); } =20 +/* MXU General purpose registers moves. */ +static inline void gen_load_mxu_gpr(TCGv t, unsigned int reg) +{ + if (reg =3D=3D 0) { + tcg_gen_movi_tl(t, 0); + } else if (reg <=3D 15) { + tcg_gen_mov_tl(t, mxu_gpr[reg - 1]); + } +} + +static inline void gen_store_mxu_gpr(TCGv t, unsigned int reg) +{ + if (reg > 0 && reg <=3D 15) { + tcg_gen_mov_tl(mxu_gpr[reg - 1], t); + } +} + +/* MXU control register moves. */ +static inline void gen_load_mxu_cr(TCGv t) +{ + tcg_gen_mov_tl(t, mxu_CR); +} + +static inline void gen_store_mxu_cr(TCGv t) +{ + tcg_gen_mov_tl(mxu_CR, t); +} + /* Moves to/from shadow registers. */ static inline void gen_load_srsgpr (int from, int to) { @@ -3807,6 +3835,51 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, } } =20 +/* MXU Instructions */ + +/* S32I2M XRa, rb - Register move from GRF to XRF */ +static void gen_mxu_s32i2m(DisasContext *ctx, uint32_t opc) +{ + TCGv t0; + uint32_t xra, rb; + + t0 =3D tcg_temp_new(); + + xra =3D extract32(ctx->opcode, 6, 5); + rb =3D extract32(ctx->opcode, 16, 5); + + gen_load_gpr(t0, rb); + if (xra <=3D 15) { + gen_store_mxu_gpr(t0, xra); + } else if (xra =3D=3D 16) { + gen_store_mxu_cr(t0); + } + + tcg_temp_free(t0); +} + +/* S32M2I XRa, rb - Register move from XRF to GRF */ +static void gen_mxu_s32m2i(DisasContext *ctx, uint32_t opc) +{ + TCGv t0; + uint32_t xra, rb; + + t0 =3D tcg_temp_new(); + + xra =3D extract32(ctx->opcode, 6, 5); + rb =3D extract32(ctx->opcode, 16, 5); + + if (xra <=3D 15) { + gen_load_mxu_gpr(t0, xra); + } else if (xra =3D=3D 16) { + gen_load_mxu_cr(t0); + } + + gen_store_gpr(t0, rb); + + tcg_temp_free(t0); +} + /* Godson integer instructions */ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) @@ -17870,6 +17943,15 @@ static void decode_opc_special2_mxu(CPUMIPSState *= env, DisasContext *ctx) case OPC_MUL: gen_arith(ctx, op1, rd, rs, rt); break; + + case OPC_MXU_S32I2M: + gen_mxu_s32i2m(ctx, op1); + break; + + case OPC_MXU_S32M2I: + gen_mxu_s32m2i(ctx, op1); + break; + default: /* Invalid */ MIPS_INVAL("special2_mxu"); generate_exception_end(ctx, EXCP_RI); @@ -17909,6 +17991,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) check_insn(ctx, INSN_LOONGSON2F); gen_loongson_integer(ctx, op1, rd, rs, rt); break; + case OPC_CLO: case OPC_CLZ: check_insn(ctx, ISA_MIPS32); --=20 2.18.0 From nobody Sat Feb 7 02:58:18 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@amazon.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535658736406175.3622446619538; Thu, 30 Aug 2018 12:52:16 -0700 (PDT) Received: from localhost ([::1]:50620 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvSzC-0007Zb-HS for importer@patchew.org; Thu, 30 Aug 2018 15:52:10 -0400 Received: from eggs.gnu.org ([208.118.235.92]:59970) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvSt3-00011E-HK for qemu-devel@nongnu.org; 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Thu, 30 Aug 2018 15:30:24 -0400 Received: (from jancraig@localhost) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Submit) id w7UJUOZV020237; Thu, 30 Aug 2018 15:30:24 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1535657429; x=1567193429; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=nymBBNziypi/2CSl+jvfGeL9aE+aI/lREK5m/qR3mGs=; b=VssyjBIQ2sP7UxVpi++QF0BH39igKKih3CdzYbYcZ3xcarEDFBsJ+QWW +CmXmUsQzdWyvRhxF6N2lTclPakflyS1U366M8iAGo2UHPesJ7P1VxZ9U L5QC2GkmhAGogP/w6Wm2/6dOk4zgOZIISU2G2s0hhOH6l6WQ3CsvHWttJ w=; X-IronPort-AV: E=Sophos;i="5.53,308,1531785600"; d="scan'208";a="695212690" To: qemu-devel@nongnu.org Date: Thu, 30 Aug 2018 15:30:15 -0400 Message-Id: <20180830193019.20104-6-jancraig@amazon.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180830193019.20104-1-jancraig@amazon.com> References: <20180830193019.20104-1-jancraig@amazon.com> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 72.21.196.25 Subject: [Qemu-devel] [PATCH v4 5/9] target/mips: Add MXU instruction S8LDD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds support for emulating the S8LDD MXU instruction. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - changed bitfield usage to extract32 - used deposit_tl instructions instead of shift and bitmask v3 - Split gen_mxu function into command specific gen_mxu_ functions v4 -Add and use MXU_OPTN3_PTN #defines -Add check for MXUEN target/mips/translate.c | 98 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 41081ee066..cfd25c3abe 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1462,6 +1462,8 @@ static TCGv_i64 msa_wr_d[64]; static TCGv mxu_gpr[15]; static TCGv mxu_CR; =20 +#define MXUEN 0x01 + #include "exec/gen-icount.h" =20 #define gen_helper_0e0i(name, arg) do { \ @@ -3837,6 +3839,16 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, =20 /* MXU Instructions */ =20 +/* MXU operand getting patterns OPTN3 */ +#define MXU_OPTN3_PTN0 0 +#define MXU_OPTN3_PTN1 1 +#define MXU_OPTN3_PTN2 2 +#define MXU_OPTN3_PTN3 3 +#define MXU_OPTN3_PTN4 4 +#define MXU_OPTN3_PTN5 5 +#define MXU_OPTN3_PTN6 6 +#define MXU_OPTN3_PTN7 7 + /* S32I2M XRa, rb - Register move from GRF to XRF */ static void gen_mxu_s32i2m(DisasContext *ctx, uint32_t opc) { @@ -3880,6 +3892,88 @@ static void gen_mxu_s32m2i(DisasContext *ctx, uint32= _t opc) tcg_temp_free(t0); } =20 +/* S8LDD XRa, rb, S8, OPTN3 - Load a byte from memory to XRF */ +static void gen_mxu_s8ldd(DisasContext *ctx, uint32_t opc) +{ + TCGv t0, t1; + TCGLabel *l0; + uint32_t xra, s8, optn3, rb; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + + l0 =3D gen_new_label(); + + xra =3D extract32(ctx->opcode, 6, 4); + s8 =3D extract32(ctx->opcode, 10, 8); + optn3 =3D extract32(ctx->opcode, 18, 3); + rb =3D extract32(ctx->opcode, 21, 5); + + gen_load_mxu_cr(t0); + tcg_gen_andi_tl(t0, t0, MXUEN); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXUEN, l0); + + gen_load_gpr(t0, rb); + tcg_gen_addi_tl(t0, t0, (int8_t)s8); + switch (optn3) { + /*XRa[7:0] =3D tmp8 */ + case MXU_OPTN3_PTN0: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, xra); + tcg_gen_deposit_tl(t0, t0, t1, 0, 8); + break; + /* XRa[15:8] =3D tmp8 */ + case MXU_OPTN3_PTN1: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, xra); + tcg_gen_deposit_tl(t0, t0, t1, 8, 8); + break; + /* XRa[23:16] =3D tmp8 */ + case MXU_OPTN3_PTN2: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, xra); + tcg_gen_deposit_tl(t0, t0, t1, 16, 8); + break; + /* XRa[31:24] =3D tmp8 */ + case MXU_OPTN3_PTN3: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, xra); + tcg_gen_deposit_tl(t0, t0, t1, 24, 8); + break; + /* XRa =3D {8'b0, tmp8, 8'b0, tmp8} */ + case MXU_OPTN3_PTN4: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_deposit_tl(t0, t1, t1, 16, 16); + break; + /* XRa =3D {tmp8, 8'b0, tmp8, 8'b0} */ + case MXU_OPTN3_PTN5: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_shli_tl(t1, t1, 8); + tcg_gen_deposit_tl(t0, t1, t1, 16, 16); + break; + /* XRa =3D {{8{sign of tmp8}}, tmp8, {8{sign of tmp8}}, tmp8} */ + case MXU_OPTN3_PTN6: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_SB); + tcg_gen_mov_tl(t0, t1); + tcg_gen_andi_tl(t0, t0, 0xFF00FFFF); + tcg_gen_shli_tl(t1, t1, 16); + tcg_gen_or_tl(t0, t0, t1); + break; + /* XRa =3D {tmp8, tmp8, tmp8, tmp8} */ + case MXU_OPTN3_PTN7: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_deposit_tl(t1, t1, t1, 8, 8); + tcg_gen_deposit_tl(t0, t1, t1, 16, 16); + break; + } + gen_store_mxu_gpr(t0, xra); + + gen_set_label(l0); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} + /* Godson integer instructions */ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) @@ -17952,6 +18046,10 @@ static void decode_opc_special2_mxu(CPUMIPSState *= env, DisasContext *ctx) gen_mxu_s32m2i(ctx, op1); break; =20 + case OPC_MXU_S8LDD: + gen_mxu_s8ldd(ctx, op1); + break; + default: /* Invalid */ MIPS_INVAL("special2_mxu"); generate_exception_end(ctx, EXCP_RI); --=20 2.18.0 From nobody Sat Feb 7 02:58:18 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@amazon.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535658674962891.8343038236746; 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X-Received-From: 52.95.49.90 Subject: [Qemu-devel] [PATCH v4 6/9] target/mips: Add MXU instruction D16MUL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds support for emulating the D16MUL instruction. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - changed bitfield usage to extract32 - used sextract_tl instructions instead of shift and ext v3 - Split gen_mxu function into command specific gen_mxu_ functions v4 - Add and use MXU_OPTN2_ #defines - Add check for MXUEN target/mips/translate.c | 70 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index cfd25c3abe..0241f1fca4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -3849,6 +3849,12 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, #define MXU_OPTN3_PTN6 6 #define MXU_OPTN3_PTN7 7 =20 +/* MXU operand getting patterns */ +#define MXU_OPTN2_WW 0 +#define MXU_OPTN2_LW 1 +#define MXU_OPTN2_HW 2 +#define MXU_OPTN2_XW 3 + /* S32I2M XRa, rb - Register move from GRF to XRF */ static void gen_mxu_s32i2m(DisasContext *ctx, uint32_t opc) { @@ -3974,6 +3980,66 @@ static void gen_mxu_s8ldd(DisasContext *ctx, uint32_= t opc) tcg_temp_free(t1); } =20 +/* D16MUL XRa, XRb, XRc, XRd, OPTN2 - Signed 16 bit pattern multiplication= */ +static void gen_mxu_d16mul(DisasContext *ctx, uint32_t opc) +{ + TCGv t0, t1, t2, t3; + TCGLabel *l0; + uint32_t xra, xrb, xrc, xrd, optn2; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + t2 =3D tcg_temp_new(); + t3 =3D tcg_temp_new(); + + l0 =3D gen_new_label(); + + xra =3D extract32(ctx->opcode, 6, 4); + xrb =3D extract32(ctx->opcode, 10, 4); + xrc =3D extract32(ctx->opcode, 14, 4); + xrd =3D extract32(ctx->opcode, 18, 4); + optn2 =3D extract32(ctx->opcode, 22, 2); + + gen_load_mxu_cr(t0); + tcg_gen_andi_tl(t0, t0, MXUEN); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXUEN, l0); + + gen_load_mxu_gpr(t1, xrb); + tcg_gen_sextract_tl(t0, t1, 0, 16); + tcg_gen_sextract_tl(t1, t1, 16, 16); + gen_load_mxu_gpr(t3, xrc); + tcg_gen_sextract_tl(t2, t3, 0, 16); + tcg_gen_sextract_tl(t3, t3, 16, 16); + + switch (optn2) { + case MXU_OPTN2_WW: /* XRB.H*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case MXU_OPTN2_LW: /* XRB.L*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case MXU_OPTN2_HW: /* XRB.H*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + case MXU_OPTN2_XW: /* XRB.L*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + } + gen_store_mxu_gpr(t3, xra); + gen_store_mxu_gpr(t2, xrd); + + gen_set_label(l0); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); +} + /* Godson integer instructions */ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) @@ -18050,6 +18116,10 @@ static void decode_opc_special2_mxu(CPUMIPSState *= env, DisasContext *ctx) gen_mxu_s8ldd(ctx, op1); break; =20 + case OPC_MXU_D16MUL: + gen_mxu_d16mul(ctx, op1); + break; + default: /* Invalid */ MIPS_INVAL("special2_mxu"); generate_exception_end(ctx, EXCP_RI); --=20 2.18.0 From nobody Sat Feb 7 02:58:18 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@amazon.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535658888204189.11729820500364; Thu, 30 Aug 2018 12:54:48 -0700 (PDT) Received: from localhost ([::1]:50635 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvT1j-00030P-44 for importer@patchew.org; Thu, 30 Aug 2018 15:54:47 -0400 Received: from eggs.gnu.org ([208.118.235.92]:60025) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvSt3-00014z-M3 for qemu-devel@nongnu.org; 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X-Received-From: 52.95.49.90 Subject: [Qemu-devel] [PATCH v4 7/9] target/mips: Add MXU instruction D16MAC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds support for emulating the D16MAC instruction. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - changed bitfield usage to extract32 - used sextract_tl instructions instead of shift and ext v3 - Split gen_mxu function into command specific gen_mxu_ functions v4 - Use MXU_OPTN2_ #defines - Add and use MXU_APTN2_ #defines - correct multi line comment format - Add check for MXUEN target/mips/translate.c | 95 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 0241f1fca4..ea6484e2db 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -3855,6 +3855,12 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, #define MXU_OPTN2_HW 2 #define MXU_OPTN2_XW 3 =20 +/* MXU acumulate patterns */ +#define MXU_APTN2_AA 0 +#define MXU_APTN2_AS 1 +#define MXU_APTN2_SA 2 +#define MXU_APTN2_SS 3 + /* S32I2M XRa, rb - Register move from GRF to XRF */ static void gen_mxu_s32i2m(DisasContext *ctx, uint32_t opc) { @@ -4040,6 +4046,91 @@ static void gen_mxu_d16mul(DisasContext *ctx, uint32= _t opc) tcg_temp_free(t3); } =20 +/* + * D16MAC XRa, XRb, XRc, XRd, APTN2, OPTN2 + * Signed 16 bit pattern multiply and accumulate + */ +static void gen_mxu_d16mac(DisasContext *ctx, uint32_t opc) +{ + TCGv t0, t1, t2, t3; + TCGLabel *l0; + uint32_t xra, xrb, xrc, xrd, optn2, aptn2; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + t2 =3D tcg_temp_new(); + t3 =3D tcg_temp_new(); + + l0 =3D gen_new_label(); + + xra =3D extract32(ctx->opcode, 6, 4); + xrb =3D extract32(ctx->opcode, 10, 4); + xrc =3D extract32(ctx->opcode, 14, 4); + xrd =3D extract32(ctx->opcode, 18, 4); + optn2 =3D extract32(ctx->opcode, 22, 2); + aptn2 =3D extract32(ctx->opcode, 24, 2); + + gen_load_mxu_cr(t0); + tcg_gen_andi_tl(t0, t0, MXUEN); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXUEN, l0); + + gen_load_mxu_gpr(t1, xrb); + tcg_gen_sextract_tl(t0, t1, 0, 16); + tcg_gen_sextract_tl(t1, t1, 16, 16); + gen_load_mxu_gpr(t3, xrc); + tcg_gen_sextract_tl(t2, t3, 0, 16); + tcg_gen_sextract_tl(t3, t3, 16, 16); + + switch (optn2) { + case MXU_OPTN2_WW: /* XRB.H*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case MXU_OPTN2_LW: /* XRB.L*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case MXU_OPTN2_HW: /* XRB.H*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + case MXU_OPTN2_XW: /* XRB.L*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + } + gen_load_mxu_gpr(t0, xra); + gen_load_mxu_gpr(t1, xrd); + + switch (aptn2) { + case MXU_APTN2_AA: + tcg_gen_add_tl(t3, t0, t3); + tcg_gen_add_tl(t2, t1, t2); + break; + case MXU_APTN2_AS: + tcg_gen_add_tl(t3, t0, t3); + tcg_gen_sub_tl(t2, t1, t2); + break; + case MXU_APTN2_SA: + tcg_gen_sub_tl(t3, t0, t3); + tcg_gen_add_tl(t2, t1, t2); + break; + case MXU_APTN2_SS: + tcg_gen_sub_tl(t3, t0, t3); + tcg_gen_sub_tl(t2, t1, t2); + break; + } + gen_store_mxu_gpr(t3, xra); + gen_store_mxu_gpr(t2, xrd); + + gen_set_label(l0); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); +} + /* Godson integer instructions */ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) @@ -18120,6 +18211,10 @@ static void decode_opc_special2_mxu(CPUMIPSState *= env, DisasContext *ctx) gen_mxu_d16mul(ctx, op1); break; =20 + case OPC_MXU_D16MAC: + gen_mxu_d16mac(ctx, op1); + break; + default: /* Invalid */ MIPS_INVAL("special2_mxu"); generate_exception_end(ctx, EXCP_RI); --=20 2.18.0 From nobody Sat Feb 7 02:58:18 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@amazon.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535658544914723.3548233709828; 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X-Received-From: 72.21.198.25 Subject: [Qemu-devel] [PATCH v4 8/9] target/mips: Add MXU instructions Q8MUL and Q8MULSU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds support for emulating the Q8MUL and Q8MULSU instructions. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - changed bitfield usage to extract32 v3 - Split gen_mxu function into command specific gen_mxu_ functions v4 - Add check for MXUEN target/mips/translate.c | 95 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index ea6484e2db..31c7342261 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4131,6 +4131,97 @@ static void gen_mxu_d16mac(DisasContext *ctx, uint32= _t opc) tcg_temp_free(t3); } =20 +/* Q8MUL XRa, XRb, XRc, XRd - Parallel unsigned 8 bit pattern multiply */ +/* Q8MULSU XRa, XRb, XRc, XRd - Parallel signed 8 bit pattern multiply */ +static void gen_mxu_q8mul(DisasContext *ctx, uint32_t opc) +{ + TCGv t0, t1, t2, t3, t4, t5, t6, t7; + TCGLabel *l0; + uint32_t xra, xrb, xrc, xrd, sel; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + t2 =3D tcg_temp_new(); + t3 =3D tcg_temp_new(); + t4 =3D tcg_temp_new(); + t5 =3D tcg_temp_new(); + t6 =3D tcg_temp_new(); + t7 =3D tcg_temp_new(); + + l0 =3D gen_new_label(); + + xra =3D extract32(ctx->opcode, 6, 4); + xrb =3D extract32(ctx->opcode, 10, 4); + xrc =3D extract32(ctx->opcode, 14, 4); + xrd =3D extract32(ctx->opcode, 18, 4); + sel =3D extract32(ctx->opcode, 22, 4); + + gen_load_mxu_cr(t0); + tcg_gen_andi_tl(t0, t0, MXUEN); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXUEN, l0); + + gen_load_mxu_gpr(t3, xrb); + gen_load_mxu_gpr(t7, xrc); + + if (sel =3D=3D 0x2) { + /* Q8MULSU */ + tcg_gen_ext8s_tl(t0, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t1, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t2, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t3, t3); + } else { + /* Q8MUL */ + tcg_gen_ext8u_tl(t0, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t1, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t2, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t3, t3); + } + + tcg_gen_ext8u_tl(t4, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t5, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t6, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t7, t7); + + tcg_gen_mul_tl(t0, t0, t4); + tcg_gen_mul_tl(t1, t1, t5); + tcg_gen_mul_tl(t2, t2, t6); + tcg_gen_mul_tl(t3, t3, t7); + + tcg_gen_andi_tl(t0, t0, 0xFFFF); + tcg_gen_andi_tl(t1, t1, 0xFFFF); + tcg_gen_andi_tl(t2, t2, 0xFFFF); + tcg_gen_andi_tl(t3, t3, 0xFFFF); + + tcg_gen_shli_tl(t1, t1, 16); + tcg_gen_shli_tl(t3, t3, 16); + + tcg_gen_or_tl(t0, t0, t1); + tcg_gen_or_tl(t1, t2, t3); + + gen_store_mxu_gpr(t0, xrd); + gen_store_mxu_gpr(t1, xra); + + gen_set_label(l0); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); + tcg_temp_free(t4); + tcg_temp_free(t5); + tcg_temp_free(t6); + tcg_temp_free(t7); +} + /* Godson integer instructions */ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) @@ -18215,6 +18306,10 @@ static void decode_opc_special2_mxu(CPUMIPSState *= env, DisasContext *ctx) gen_mxu_d16mac(ctx, op1); break; =20 + case OPC_MXU_Q8MUL: + gen_mxu_q8mul(ctx, op1); + break; + default: /* Invalid */ MIPS_INVAL("special2_mxu"); generate_exception_end(ctx, EXCP_RI); --=20 2.18.0 From nobody Sat Feb 7 02:58:18 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@amazon.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535658686492531.0739593829178; Thu, 30 Aug 2018 12:51:26 -0700 (PDT) Received: from localhost ([::1]:50617 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvSyP-0006wn-EM for importer@patchew.org; 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X-Received-From: 207.171.184.25 Subject: [Qemu-devel] [PATCH v4 9/9] target/mips: Add MXU instructions S32LDD and S32LDDR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds support for emulating the S32LDD and S32LDDR MXU instructions. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - changed bitfield usage to extract32 v3 - Split gen_mxu function into command specific gen_mxu_ functions v4 - Add check for MXUEN target/mips/translate.c | 49 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 31c7342261..297f913d36 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4222,6 +4222,51 @@ static void gen_mxu_q8mul(DisasContext *ctx, uint32_= t opc) tcg_temp_free(t7); } =20 +/* S32LDD XRa, rb, S12 - Load a word from memory to XRF + * S32LDDR XRa, rb, S12 - Load a word from memory to XRF, + * reversed byte sequence */ +static void gen_mxu_s32ldd(DisasContext *ctx, uint32_t opc) +{ + TCGv t0, t1; + TCGLabel *l0; + uint32_t xra, s12, sel, rb; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + + l0 =3D gen_new_label(); + + xra =3D extract32(ctx->opcode, 6, 4); + s12 =3D extract32(ctx->opcode, 10, 10); + sel =3D extract32(ctx->opcode, 20, 1); + rb =3D extract32(ctx->opcode, 21, 5); + + gen_load_mxu_cr(t0); + tcg_gen_andi_tl(t0, t0, MXUEN); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXUEN, l0); + + gen_load_gpr(t0, rb); + + tcg_gen_movi_tl(t1, s12); + tcg_gen_shli_tl(t1, t1, 2); + if (s12 & 0x200) { + tcg_gen_ori_tl(t1, t1, 0xFFFFF000); + } + tcg_gen_add_tl(t1, t0, t1); + tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_SL); + + if (sel =3D=3D 1) { + /* S32LDDR */ + tcg_gen_bswap32_tl(t1, t1); + } + gen_store_mxu_gpr(t1, xra); + + gen_set_label(l0); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} + /* Godson integer instructions */ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) @@ -18310,6 +18355,10 @@ static void decode_opc_special2_mxu(CPUMIPSState *= env, DisasContext *ctx) gen_mxu_q8mul(ctx, op1); break; =20 + case OPC_MXU_S32LDD: + gen_mxu_s32ldd(ctx, op1); + break; + default: /* Invalid */ MIPS_INVAL("special2_mxu"); generate_exception_end(ctx, EXCP_RI); --=20 2.18.0