From nobody Wed Nov 5 16:33:49 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535632236936313.4928138064164; Thu, 30 Aug 2018 05:30:36 -0700 (PDT) Received: from localhost ([::1]:48662 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvM5r-0001WY-S8 for importer@patchew.org; Thu, 30 Aug 2018 08:30:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42142) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvM3W-00008O-4c for qemu-devel@nongnu.org; Thu, 30 Aug 2018 08:28:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fvM3T-0000TR-FC for qemu-devel@nongnu.org; Thu, 30 Aug 2018 08:28:09 -0400 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:35134 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fvM3T-0000Rl-8h; Thu, 30 Aug 2018 08:28:07 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E40F080825A9; Thu, 30 Aug 2018 12:28:06 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-143.ams2.redhat.com [10.36.117.143]) by smtp.corp.redhat.com (Postfix) with ESMTP id CC89D2166B41; Thu, 30 Aug 2018 12:28:03 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Thu, 30 Aug 2018 14:27:50 +0200 Message-Id: <20180830122756.13991-4-david@redhat.com> In-Reply-To: <20180830122756.13991-1-david@redhat.com> References: <20180830122756.13991-1-david@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.6 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.8]); Thu, 30 Aug 2018 12:28:06 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.8]); Thu, 30 Aug 2018 12:28:06 +0000 (UTC) for IP:'10.11.54.6' DOMAIN:'int-mx06.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'david@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [PATCH v2 3/9] s390x/tcg: store in the TB flags if AFP is enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , David Hildenbrand , Cornelia Huck , Alexander Graf , Christian Borntraeger , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We exit the TB when changing the control registers, so just like PSW bits, this should always be consistent for a TB. Using the PSW bit semantic makes things a lot easier compared to manually defining the spare, shifted bits. Reviewed-by: Richard Henderson Signed-off-by: David Hildenbrand --- target/s390x/cpu.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 5e50c3a303..8c2320e882 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -255,6 +255,7 @@ extern const struct VMStateDescription vmstate_s390_cpu; =20 /* PSW defines */ #undef PSW_MASK_PER +#undef PSW_MASK_UNUSED_2 #undef PSW_MASK_DAT #undef PSW_MASK_IO #undef PSW_MASK_EXT @@ -273,6 +274,7 @@ extern const struct VMStateDescription vmstate_s390_cpu; #undef PSW_MASK_ESA_ADDR =20 #define PSW_MASK_PER 0x4000000000000000ULL +#define PSW_MASK_UNUSED_2 0x2000000000000000ULL #define PSW_MASK_DAT 0x0400000000000000ULL #define PSW_MASK_IO 0x0200000000000000ULL #define PSW_MASK_EXT 0x0100000000000000ULL @@ -318,6 +320,9 @@ extern const struct VMStateDescription vmstate_s390_cpu; #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK= _PSTATE \ | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK= _32) =20 +/* we'll use some unused PSW positions to store CR flags in tb flags */ +#define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT) + /* Control register 0 bits */ #define CR0_LOWPROT 0x0000000010000000ULL #define CR0_SECONDARY 0x0000000004000000ULL @@ -364,6 +369,9 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState* = env, target_ulong *pc, *pc =3D env->psw.addr; *cs_base =3D env->ex_value; *flags =3D (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; + if (env->cregs[0] & CR0_AFP) { + *flags |=3D FLAG_MASK_AFP; + } } =20 /* PER bits from control register 9 */ --=20 2.17.1