From nobody Wed Nov 5 16:39:41 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@amazon.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535461884783803.4086940535193; Tue, 28 Aug 2018 06:11:24 -0700 (PDT) Received: from localhost ([::1]:38138 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fudmF-0004kc-Do for importer@patchew.org; Tue, 28 Aug 2018 09:11:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52580) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fudfg-0006gP-4p for qemu-devel@nongnu.org; Tue, 28 Aug 2018 09:04:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fudfZ-0006Yi-Oo for qemu-devel@nongnu.org; Tue, 28 Aug 2018 09:04:35 -0400 Received: from smtp-fw-9102.amazon.com ([207.171.184.29]:59075) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1fudfY-0006Ry-7Y for qemu-devel@nongnu.org; Tue, 28 Aug 2018 09:04:29 -0400 Received: from sea3-co-svc-lb6-vlan3.sea.amazon.com (HELO email-inbound-relay-1a-16acd5e0.us-east-1.amazon.com) ([10.47.22.38]) by smtp-border-fw-out-9102.sea19.amazon.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 28 Aug 2018 13:01:58 +0000 Received: from ua08cfde8192f59f8a244.ant.amazon.com (iad7-ws-svc-lb50-vlan2.amazon.com [10.0.93.210]) by email-inbound-relay-1a-16acd5e0.us-east-1.amazon.com (8.14.7/8.14.7) with ESMTP id w7SD0oDH104462 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 28 Aug 2018 13:00:51 GMT Received: from ua08cfde8192f59f8a244.ant.amazon.com (localhost [127.0.0.1]) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id w7SD0oaD026535; Tue, 28 Aug 2018 09:00:50 -0400 Received: (from jancraig@localhost) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Submit) id w7SD0oQ3026534; Tue, 28 Aug 2018 09:00:50 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1535461468; x=1566997468; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=w0BVeB1mBRWCjQMo1Mz6/jNPv+etOrdlaapdpu0JDkg=; b=jDNA59jtgwEMl4OkoxGGLxVBNVauklmLqbOXQGnP9NCqKJVbU1CbOyK3 rpg/IYW7C4BEwXdILjRsikmd4VXayROiggJA2Ebe8ahob+8b36t59HZ/r XG6BoucE82SHBtWb6xwueT0j6sWTtLkoH1aiZM7hGvBRR33HKJEgeadEF Q=; X-IronPort-AV: E=Sophos;i="5.53,299,1531785600"; d="scan'208";a="628441007" To: qemu-devel@nongnu.org Date: Tue, 28 Aug 2018 09:00:41 -0400 Message-Id: <20180828130041.26445-9-jancraig@amazon.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180828130041.26445-1-jancraig@amazon.com> References: <20180828130041.26445-1-jancraig@amazon.com> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 207.171.184.29 Subject: [Qemu-devel] [PATCH v3 8/8] target/mips: Add MXU instructions S32LDD and S32LDDR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds support for emulating the S32LDD and S32LDDR MXU instructions. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - changed bitfield usage to extract32 v3 - Split gen_mxu function into command specific gen_mxu_ functions target/mips/translate.c | 47 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index a28ea124c2..1ddc9f04e8 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4123,6 +4123,42 @@ static void gen_mxu_q8mul(DisasContext *ctx, uint32_= t opc) tcg_temp_free(t7); } =20 +/* S32LDD XRa, rb, S12 - Load a word from memory to XRF + * S32LDDR XRa, rb, S12 - Load a word from memory to XRF, + * reversed byte sequence */ +static void gen_mxu_s32ldd(DisasContext *ctx, uint32_t opc) +{ + TCGv t0, t1; + uint32_t xra, s12, sel, rb; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + + xra =3D extract32(ctx->opcode, 6, 4); + s12 =3D extract32(ctx->opcode, 10, 10); + sel =3D extract32(ctx->opcode, 20, 1); + rb =3D extract32(ctx->opcode, 21, 5); + + gen_load_gpr(t0, rb); + + tcg_gen_movi_tl(t1, s12); + tcg_gen_shli_tl(t1, t1, 2); + if (s12 & 0x200) { + tcg_gen_ori_tl(t1, t1, 0xFFFFF000); + } + tcg_gen_add_tl(t1, t0, t1); + tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_SL); + + if (sel =3D=3D 1) { + /* S32LDDR */ + tcg_gen_bswap32_tl(t1, t1); + } + gen_store_mxu_gpr(t1, xra); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} + /* Godson integer instructions */ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) @@ -18212,7 +18248,6 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) break; case OPC_DIV_G_2F_MXU_S32LDI: case OPC_DIVU_G_2F_MXU_S32LDIV: - case OPC_MULT_G_2F_MXU_S32LDD: case OPC_MULTU_G_2F_MXU_S32LDDV: case OPC_MOD_G_2F_MXU_Q8ADDE: case OPC_MODU_G_2F: @@ -18244,6 +18279,16 @@ static void decode_opc_special2_legacy(CPUMIPSStat= e *env, DisasContext *ctx) gen_mxu_q8mul(ctx, op1); break; =20 + case OPC_MULT_G_2F_MXU_S32LDD: + /* There is an overlap of opcodes between Loongson2F and MXU */ + if (ctx->insn_flags & INSN_LOONGSON2F) { + check_insn(ctx, INSN_LOONGSON2F); + gen_loongson_integer(ctx, op1, rd, rs, rt); + } else { + gen_mxu_s32ldd(ctx, op1); + } + break; + case OPC_CLO: case OPC_CLZ: check_insn(ctx, ISA_MIPS32); --=20 2.18.0