From nobody Wed Nov 5 16:39:39 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@amazon.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535461753981482.18699202702965; Tue, 28 Aug 2018 06:09:13 -0700 (PDT) Received: from localhost ([::1]:38116 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fudk4-0002vW-GJ for importer@patchew.org; Tue, 28 Aug 2018 09:09:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52548) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fudfc-0006d9-8N for qemu-devel@nongnu.org; Tue, 28 Aug 2018 09:04:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fudfW-0006Sn-MP for qemu-devel@nongnu.org; Tue, 28 Aug 2018 09:04:32 -0400 Received: from smtp-fw-33001.amazon.com ([207.171.190.10]:25109) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1fudfW-0006Ql-C2 for qemu-devel@nongnu.org; Tue, 28 Aug 2018 09:04:26 -0400 Received: from sea3-co-svc-lb6-vlan2.sea.amazon.com (HELO email-inbound-relay-1e-62350142.us-east-1.amazon.com) ([10.47.22.34]) by smtp-border-fw-out-33001.sea14.amazon.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 28 Aug 2018 13:02:06 +0000 Received: from ua08cfde8192f59f8a244.ant.amazon.com (iad7-ws-svc-lb50-vlan3.amazon.com [10.0.93.214]) by email-inbound-relay-1e-62350142.us-east-1.amazon.com (8.14.7/8.14.7) with ESMTP id w7SD0op4068263 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 28 Aug 2018 13:00:51 GMT Received: from ua08cfde8192f59f8a244.ant.amazon.com (localhost [127.0.0.1]) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id w7SD0ncc026523; Tue, 28 Aug 2018 09:00:49 -0400 Received: (from jancraig@localhost) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Submit) id w7SD0nTP026522; Tue, 28 Aug 2018 09:00:49 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1535461466; x=1566997466; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=EKLGPYYtEQhPexh2nh/YSsm1vpyIRy9cikJLF4naruE=; b=k/zM8fOBMLEv9haI9vb49RT0uXl6HCLaVTgFI0HM6z4U6Y0R2+8C7+ZA KG9FKIZD6bWDpfiPX22uB9ZJAUmVhRXxX6LEqLwMum+Mnv1p8UnLmTAqL OXcTjxDIwp2J5umd36Sf3pJ5PUg/Nt/CDV2hZKSMnXKRFpNQ+4wb27bfJ M=; X-IronPort-AV: E=Sophos;i="5.53,299,1531785600"; d="scan'208";a="750966976" To: qemu-devel@nongnu.org Date: Tue, 28 Aug 2018 09:00:38 -0400 Message-Id: <20180828130041.26445-6-jancraig@amazon.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180828130041.26445-1-jancraig@amazon.com> References: <20180828130041.26445-1-jancraig@amazon.com> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 207.171.190.10 Subject: [Qemu-devel] [PATCH v3 5/8] target/mips: Add MXU instruction D16MUL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds support for emulating the D16MUL instruction. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - changed bitfield usage to extract32 - used sextract_tl instructions instead of shift and ext v3 - Split gen_mxu function into command specific gen_mxu_ functions target/mips/translate.c | 55 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 024e48baf6..f693e45203 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -3916,6 +3916,57 @@ static void gen_mxu_s8ldd(DisasContext *ctx, uint32_= t opc) tcg_temp_free(t1); } =20 +/* D16MUL XRa, XRb, XRc, XRd, OPTN2 - Signed 16 bit pattern multiplication= */ +static void gen_mxu_d16mul(DisasContext *ctx, uint32_t opc) +{ + TCGv t0, t1, t2, t3; + uint32_t xra, xrb, xrc, xrd, optn2; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + t2 =3D tcg_temp_new(); + t3 =3D tcg_temp_new(); + + xra =3D extract32(ctx->opcode, 6, 4); + xrb =3D extract32(ctx->opcode, 10, 4); + xrc =3D extract32(ctx->opcode, 14, 4); + xrd =3D extract32(ctx->opcode, 18, 4); + optn2 =3D extract32(ctx->opcode, 22, 2); + + gen_load_mxu_gpr(t1, xrb); + tcg_gen_sextract_tl(t0, t1, 0, 16); + tcg_gen_sextract_tl(t1, t1, 16, 16); + gen_load_mxu_gpr(t3, xrc); + tcg_gen_sextract_tl(t2, t3, 0, 16); + tcg_gen_sextract_tl(t3, t3, 16, 16); + + switch (optn2) { + case 0: /* XRB.H*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case 1: /* XRB.L*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case 2: /* XRB.H*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + case 3: /* XRB.L*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + } + gen_store_mxu_gpr(t3, xra); + gen_store_mxu_gpr(t2, xrd); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); +} + /* Godson integer instructions */ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) @@ -18025,6 +18076,10 @@ static void decode_opc_special2_legacy(CPUMIPSStat= e *env, DisasContext *ctx) gen_mxu_s8ldd(ctx, op1); break; =20 + case OPC_MXU_D16MUL: + gen_mxu_d16mul(ctx, op1); + break; + case OPC_CLO: case OPC_CLZ: check_insn(ctx, ISA_MIPS32); --=20 2.18.0