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X-Received-From: 72.21.196.25 Subject: [Qemu-devel] [PATCH v3 3/8] target/mips: Add MXU instructions S32I2M and S32M2I X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This commit makes the MXU registers and the utility functions for reading/writing to them. This is required for full MXU instruction support. Adds support for emulating the S32I2M and S32M2I MXU instructions. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - Fix checkpatch.pl errors - remove mips64 ifdef - changed bitfield usage to extract32 - squashed register addition patch into this one v3 - Split register addition and opcode enum definition into seperate patc= hes - Split gen_mxu function into command specific gen_mxu_ functions target/mips/translate.c | 62 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index ae6b16ecd7..f6991aa8ef 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1610,6 +1610,23 @@ static inline void gen_store_gpr (TCGv t, int reg) tcg_gen_mov_tl(cpu_gpr[reg], t); } =20 +/* MXU General purpose registers moves. */ +static inline void gen_load_mxu_gpr(TCGv t, int reg) +{ + if (reg =3D=3D 0) { + tcg_gen_movi_tl(t, 0); + } else { + tcg_gen_mov_tl(t, mxu_gpr[reg - 1]); + } +} + +static inline void gen_store_mxu_gpr(TCGv t, int reg) +{ + if (reg !=3D 0) { + tcg_gen_mov_tl(mxu_gpr[reg - 1], t); + } +} + /* Moves to/from shadow registers. */ static inline void gen_load_srsgpr (int from, int to) { @@ -3798,6 +3815,42 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, } } =20 +/* MXU Instructions */ + +/* S32I2M XRa, rb - Register move from GRF to XRF */ +static void gen_mxu_s32i2m(DisasContext *ctx, uint32_t opc) +{ + TCGv t0; + uint32_t xra, rb; + + t0 =3D tcg_temp_new(); + + xra =3D extract32(ctx->opcode, 6, 5); + rb =3D extract32(ctx->opcode, 16, 5); + + gen_load_gpr(t0, rb); + gen_store_mxu_gpr(t0, xra); + + tcg_temp_free(t0); +} + +/* S32M2I XRa, rb - Register move from XRF to GRF */ +static void gen_mxu_s32m2i(DisasContext *ctx, uint32_t opc) +{ + TCGv t0; + uint32_t xra, rb; + + t0 =3D tcg_temp_new(); + + xra =3D extract32(ctx->opcode, 6, 5); + rb =3D extract32(ctx->opcode, 16, 5); + + gen_load_mxu_gpr(t0, xra); + gen_store_gpr(t0, rb); + + tcg_temp_free(t0); +} + /* Godson integer instructions */ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) @@ -17894,6 +17947,15 @@ static void decode_opc_special2_legacy(CPUMIPSStat= e *env, DisasContext *ctx) check_insn(ctx, INSN_LOONGSON2F); gen_loongson_integer(ctx, op1, rd, rs, rt); break; + + case OPC_MXU_S32I2M: + gen_mxu_s32i2m(ctx, op1); + break; + + case OPC_MXU_S32M2I: + gen_mxu_s32m2i(ctx, op1); + break; + case OPC_CLO: case OPC_CLZ: check_insn(ctx, ISA_MIPS32); --=20 2.18.0