From nobody Sat Feb 7 07:12:05 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@amazon.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535461540116446.5550211093589; Tue, 28 Aug 2018 06:05:40 -0700 (PDT) Received: from localhost ([::1]:38087 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fudgg-00074T-HB for importer@patchew.org; Tue, 28 Aug 2018 09:05:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50683) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fudca-0002k9-SE for qemu-devel@nongnu.org; Tue, 28 Aug 2018 09:01:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fudc5-0000bG-SQ for qemu-devel@nongnu.org; Tue, 28 Aug 2018 09:00:58 -0400 Received: from smtp-fw-6001.amazon.com ([52.95.48.154]:50160) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1fudc5-0000Wt-Nh for qemu-devel@nongnu.org; Tue, 28 Aug 2018 09:00:53 -0400 Received: from iad6-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-1e-c7c08562.us-east-1.amazon.com) ([10.124.125.6]) by smtp-border-fw-out-6001.iad6.amazon.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 28 Aug 2018 13:00:50 +0000 Received: from ua08cfde8192f59f8a244.ant.amazon.com (iad7-ws-svc-lb50-vlan2.amazon.com [10.0.93.210]) by email-inbound-relay-1e-c7c08562.us-east-1.amazon.com (8.14.7/8.14.7) with ESMTP id w7SD0mCl093047 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 28 Aug 2018 13:00:50 GMT Received: from ua08cfde8192f59f8a244.ant.amazon.com (localhost [127.0.0.1]) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id w7SD0mQe026507; Tue, 28 Aug 2018 09:00:48 -0400 Received: (from jancraig@localhost) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Submit) id w7SD0m99026506; Tue, 28 Aug 2018 09:00:48 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1535461253; x=1566997253; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=87gnUScbOmEe17EcCsgpL1nMtfsFcfPMIaTKYVTh6ac=; b=q4BXqsJgvFzFaiCPCt7zZ5njxbrHhouZBSl6zdeN6p2nFA5W7XI22dYq omc/xrEmx0uOgWwFpoYiOiBimQHSywdKAkxZTLPeUWsX3JiJNdXgHLCUC n+WaIxY0YQcpwxGRUVzVOcGeR9ObMPepYHHkwdrGNCmRUDEkwbp7vMdBW o=; X-IronPort-AV: E=Sophos;i="5.53,299,1531785600"; d="scan'208";a="354245809" To: qemu-devel@nongnu.org Date: Tue, 28 Aug 2018 09:00:34 -0400 Message-Id: <20180828130041.26445-2-jancraig@amazon.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180828130041.26445-1-jancraig@amazon.com> References: <20180828130041.26445-1-jancraig@amazon.com> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 52.95.48.154 Subject: [Qemu-devel] [PATCH v3 1/8] target/mips: Introduce MXU registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Define and initialize the 16 MXU registers. Signed-off-by: Craig Janeczek --- v1 - NA v2 - NA v3 - Initial patch, split out from prior first patch target/mips/cpu.h | 1 + target/mips/translate.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 009202cf64..4b2948a2c8 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -170,6 +170,7 @@ struct TCState { MSACSR_FS_MASK) =20 float_status msa_fp_status; + target_ulong mxu_gpr[16]; }; =20 typedef struct CPUMIPSState CPUMIPSState; diff --git a/target/mips/translate.c b/target/mips/translate.c index bdd880bb77..416488b383 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1398,6 +1398,9 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31; static TCGv_i64 fpu_f64[32]; static TCGv_i64 msa_wr_d[64]; =20 +/* MXU registers */ +static TCGv mxu_gpr[16]; + #include "exec/gen-icount.h" =20 #define gen_helper_0e0i(name, arg) do { \ @@ -1517,6 +1520,13 @@ static const char * const msaregnames[] =3D { "w30.d0", "w30.d1", "w31.d0", "w31.d1", }; =20 +static const char * const mxuregnames[] =3D { + "XR1", "XR2", "XR3", "XR4", "XR5", + "XR6", "XR7", "XR8", "XR9", "XR10", + "XR11", "XR12", "XR13", "XR14", "XR15", + "XR16", +}; + #define LOG_DISAS(...) = \ do { = \ if (MIPS_DEBUG_DISAS) { = \ @@ -20742,6 +20752,12 @@ void mips_tcg_init(void) fpu_fcr31 =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMIPSState, active_fpu.f= cr31), "fcr31"); + + for (i =3D 0; i < 16; i++) + mxu_gpr[i] =3D tcg_global_mem_new(cpu_env, + offsetof(CPUMIPSState, + active_tc.mxu_gpr[i]), + mxuregnames[i]); } =20 #include "translate_init.inc.c" --=20 2.18.0