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X-Received-From: 207.171.190.10 Subject: [Qemu-devel] [PATCH v2 4/6] target/mips: Add MXU instruction D16MAC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds support for emulating the D16MAC instruction. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - changed bitfield usage to extract32 - used sextract_tl instructions instead of shift and ext target/mips/translate.c | 62 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 8a6b4f2899..7d37567652 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -366,6 +366,7 @@ enum { OPC_DCLO =3D 0x25 | OPC_SPECIAL2, /* MXU */ OPC_MXU_D16MUL =3D 0x08 | OPC_SPECIAL2, + OPC_MXU_D16MAC =3D 0x0A | OPC_SPECIAL2, OPC_MXU_S8LDD =3D 0x22 | OPC_SPECIAL2, OPC_MXU_S32I2M =3D 0x2F | OPC_SPECIAL2, OPC_MXU_S32M2I =3D 0x2E | OPC_SPECIAL2, @@ -3774,7 +3775,7 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, static void gen_mxu(DisasContext *ctx, uint32_t opc) { TCGv t0, t1, t2, t3; - uint32_t rb, xra, xrb, xrc, xrd, s8, sel, optn2, optn3; + uint32_t rb, xra, xrb, xrc, xrd, s8, sel, optn2, optn3, aptn2; =20 t0 =3D tcg_temp_new(); t1 =3D tcg_temp_new(); @@ -3892,6 +3893,64 @@ static void gen_mxu(DisasContext *ctx, uint32_t opc) gen_store_mxu_gpr(t3, xra); gen_store_mxu_gpr(t2, xrd); break; + + case OPC_MXU_D16MAC: + xra =3D extract32(ctx->opcode, 6, 4); + xrb =3D extract32(ctx->opcode, 10, 4); + xrc =3D extract32(ctx->opcode, 14, 4); + xrd =3D extract32(ctx->opcode, 18, 4); + optn2 =3D extract32(ctx->opcode, 22, 2); + aptn2 =3D extract32(ctx->opcode, 24, 2); + + gen_load_mxu_gpr(t1, xrb); + tcg_gen_sextract_tl(t0, t1, 0, 16); + tcg_gen_sextract_tl(t1, t1, 16, 16); + gen_load_mxu_gpr(t3, xrc); + tcg_gen_sextract_tl(t2, t3, 0, 16); + tcg_gen_sextract_tl(t3, t3, 16, 16); + + switch (optn2) { + case 0: /* XRB.H*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case 1: /* XRB.L*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case 2: /* XRB.H*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + case 3: /* XRB.L*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + } + gen_load_mxu_gpr(t0, xra); + gen_load_mxu_gpr(t1, xrd); + + switch (aptn2) { + case 0: + tcg_gen_add_tl(t3, t0, t3); + tcg_gen_add_tl(t2, t1, t2); + break; + case 1: + tcg_gen_add_tl(t3, t0, t3); + tcg_gen_sub_tl(t2, t1, t2); + break; + case 2: + tcg_gen_sub_tl(t3, t0, t3); + tcg_gen_add_tl(t2, t1, t2); + break; + case 3: + tcg_gen_sub_tl(t3, t0, t3); + tcg_gen_sub_tl(t2, t1, t2); + break; + } + gen_store_mxu_gpr(t3, xra); + gen_store_mxu_gpr(t2, xrd); + break; } =20 tcg_temp_free(t0); @@ -17985,6 +18044,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) case OPC_MXU_S32M2I: case OPC_MXU_S8LDD: case OPC_MXU_D16MUL: + case OPC_MXU_D16MAC: gen_mxu(ctx, op1); break; =20 --=20 2.18.0