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X-Received-From: 72.21.196.25 Subject: [Qemu-devel] [PATCH v2 2/6] target/mips: Add MXU instruction S8LDD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds support for emulating the S8LDD MXU instruction. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - changed bitfield usage to extract32 - used deposit_tl instructions instead of shift and bitmask target/mips/translate.c | 62 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 60 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index ef819d67e0..f5725d8eda 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -365,6 +365,7 @@ enum { OPC_DCLZ =3D 0x24 | OPC_SPECIAL2, OPC_DCLO =3D 0x25 | OPC_SPECIAL2, /* MXU */ + OPC_MXU_S8LDD =3D 0x22 | OPC_SPECIAL2, OPC_MXU_S32I2M =3D 0x2F | OPC_SPECIAL2, OPC_MXU_S32M2I =3D 0x2E | OPC_SPECIAL2, /* Special */ @@ -3771,10 +3772,11 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, /* MXU Instructions */ static void gen_mxu(DisasContext *ctx, uint32_t opc) { - TCGv t0; - uint32_t xra, rb; + TCGv t0, t1; + uint32_t xra, rb, s8, optn3; =20 t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); =20 switch (opc) { case OPC_MXU_S32I2M: @@ -3792,9 +3794,64 @@ static void gen_mxu(DisasContext *ctx, uint32_t opc) gen_load_mxu_gpr(t0, xra); gen_store_gpr(t0, rb); break; + + case OPC_MXU_S8LDD: + xra =3D extract32(ctx->opcode, 6, 4); + s8 =3D extract32(ctx->opcode, 10, 8); + optn3 =3D extract32(ctx->opcode, 18, 3); + rb =3D extract32(ctx->opcode, 21, 5); + + gen_load_gpr(t0, rb); + tcg_gen_addi_tl(t0, t0, (int8_t)s8); + switch (optn3) { + case 0: /*XRa[7:0] =3D tmp8 */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, xra); + tcg_gen_deposit_tl(t0, t0, t1, 0, 8); + break; + case 1: /* XRa[15:8] =3D tmp8 */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, xra); + tcg_gen_deposit_tl(t0, t0, t1, 8, 8); + break; + case 2: /* XRa[23:16] =3D tmp8 */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, xra); + tcg_gen_deposit_tl(t0, t0, t1, 16, 8); + break; + case 3: /* XRa[31:24] =3D tmp8 */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, xra); + tcg_gen_deposit_tl(t0, t0, t1, 24, 8); + break; + case 4: /* XRa =3D {8'b0, tmp8, 8'b0, tmp8} */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_deposit_tl(t0, t1, t1, 16, 16); + break; + case 5: /* XRa =3D {tmp8, 8'b0, tmp8, 8'b0} */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_shli_tl(t1, t1, 8); + tcg_gen_deposit_tl(t0, t1, t1, 16, 16); + break; + case 6: /* XRa =3D {{8{sign of tmp8}}, tmp8, {8{sign of tmp8}}, tm= p8} */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_SB); + tcg_gen_mov_tl(t0, t1); + tcg_gen_andi_tl(t0, t0, 0xFF00FFFF); + tcg_gen_shli_tl(t1, t1, 16); + tcg_gen_or_tl(t0, t0, t1); + break; + case 7: /* XRa =3D {tmp8, tmp8, tmp8, tmp8} */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_deposit_tl(t1, t1, t1, 8, 8); + tcg_gen_deposit_tl(t0, t1, t1, 16, 16); + break; + } + gen_store_mxu_gpr(t0, xra); + break; } =20 tcg_temp_free(t0); + tcg_temp_free(t1); } =20 /* Godson integer instructions */ @@ -17880,6 +17937,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) =20 case OPC_MXU_S32I2M: case OPC_MXU_S32M2I: + case OPC_MXU_S8LDD: gen_mxu(ctx, op1); break; =20 --=20 2.18.0