From nobody Mon Feb 9 00:00:49 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@amazon.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535381040665283.28649300437723; Mon, 27 Aug 2018 07:44:00 -0700 (PDT) Received: from localhost ([::1]:53561 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fuIkD-0007CP-S7 for importer@patchew.org; Mon, 27 Aug 2018 10:43:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46199) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fuIiN-0006CA-0v for qemu-devel@nongnu.org; Mon, 27 Aug 2018 10:42:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fuIiI-00026e-Tl for qemu-devel@nongnu.org; Mon, 27 Aug 2018 10:41:58 -0400 Received: from smtp-fw-33001.amazon.com ([207.171.190.10]:30130) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1fuIiI-000260-H2 for qemu-devel@nongnu.org; Mon, 27 Aug 2018 10:41:54 -0400 Received: from sea3-co-svc-lb6-vlan2.sea.amazon.com (HELO email-inbound-relay-1a-7d76a15f.us-east-1.amazon.com) ([10.47.22.34]) by smtp-border-fw-out-33001.sea14.amazon.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 27 Aug 2018 14:39:33 +0000 Received: from ua08cfde8192f59f8a244.ant.amazon.com (iad7-ws-svc-lb50-vlan2.amazon.com [10.0.93.210]) by email-inbound-relay-1a-7d76a15f.us-east-1.amazon.com (8.14.7/8.14.7) with ESMTP id w7REcK61076283 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 27 Aug 2018 14:38:21 GMT Received: from ua08cfde8192f59f8a244.ant.amazon.com (localhost [127.0.0.1]) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id w7REcKI7025134; Mon, 27 Aug 2018 10:38:20 -0400 Received: (from jancraig@localhost) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Submit) id w7REcKJd025133; Mon, 27 Aug 2018 10:38:20 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1535380914; x=1566916914; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=y6ev9x/wZ7hu4RvN064OGvMHSS1peu1u/tFErNhIOic=; b=qddAvzl9kRO0bNKnOSDzQ0JXKt07zn2fOdgPJbnv2OX6nrUyUNI5pHzk U9c/6bHLyccAJscF+kkI6YYVjCJYzVBUctVPCCvZpvX5DFBR/rnKCgRKU dkiOxnCk+U1Co4dR+jABmV5O8Ju74qyjFoxPZ19z8EOcDCovgNUI0vb8H o=; X-IronPort-AV: E=Sophos;i="5.53,295,1531785600"; d="scan'208";a="750831319" To: qemu-devel@nongnu.org Date: Mon, 27 Aug 2018 10:38:01 -0400 Message-Id: <20180827143806.25048-2-jancraig@amazon.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180827143806.25048-1-jancraig@amazon.com> References: <20180827143806.25048-1-jancraig@amazon.com> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 207.171.190.10 Subject: [Qemu-devel] [PATCH v2 1/6] target/mips: Add MXU instructions S32I2M and S32M2I X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This commit makes the MXU registers and the utility functions for reading/writing to them. This is required for full MXU instruction support. Adds support for emulating the S32I2M and S32M2I MXU instructions. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - Fix checkpatch.pl errors - remove mips64 ifdef - changed bitfield usage to extract32 - squashed register addition patch into this one target/mips/cpu.h | 1 + target/mips/translate.c | 71 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 009202cf64..4b2948a2c8 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -170,6 +170,7 @@ struct TCState { MSACSR_FS_MASK) =20 float_status msa_fp_status; + target_ulong mxu_gpr[16]; }; =20 typedef struct CPUMIPSState CPUMIPSState; diff --git a/target/mips/translate.c b/target/mips/translate.c index bdd880bb77..ef819d67e0 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -364,6 +364,9 @@ enum { OPC_CLO =3D 0x21 | OPC_SPECIAL2, OPC_DCLZ =3D 0x24 | OPC_SPECIAL2, OPC_DCLO =3D 0x25 | OPC_SPECIAL2, + /* MXU */ + OPC_MXU_S32I2M =3D 0x2F | OPC_SPECIAL2, + OPC_MXU_S32M2I =3D 0x2E | OPC_SPECIAL2, /* Special */ OPC_SDBBP =3D 0x3F | OPC_SPECIAL2, }; @@ -1398,6 +1401,9 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31; static TCGv_i64 fpu_f64[32]; static TCGv_i64 msa_wr_d[64]; =20 +/* MXU registers */ +static TCGv mxu_gpr[16]; + #include "exec/gen-icount.h" =20 #define gen_helper_0e0i(name, arg) do { \ @@ -1517,6 +1523,13 @@ static const char * const msaregnames[] =3D { "w30.d0", "w30.d1", "w31.d0", "w31.d1", }; =20 +static const char * const mxuregnames[] =3D { + "XR1", "XR2", "XR3", "XR4", "XR5", + "XR6", "XR7", "XR8", "XR9", "XR10", + "XR11", "XR12", "XR13", "XR14", "XR15", + "XR16", +}; + #define LOG_DISAS(...) = \ do { = \ if (MIPS_DEBUG_DISAS) { = \ @@ -1550,6 +1563,23 @@ static inline void gen_store_gpr (TCGv t, int reg) tcg_gen_mov_tl(cpu_gpr[reg], t); } =20 +/* MXU General purpose registers moves. */ +static inline void gen_load_mxu_gpr(TCGv t, int reg) +{ + if (reg =3D=3D 0) { + tcg_gen_movi_tl(t, 0); + } else { + tcg_gen_mov_tl(t, mxu_gpr[reg - 1]); + } +} + +static inline void gen_store_mxu_gpr(TCGv t, int reg) +{ + if (reg !=3D 0) { + tcg_gen_mov_tl(mxu_gpr[reg - 1], t); + } +} + /* Moves to/from shadow registers. */ static inline void gen_load_srsgpr (int from, int to) { @@ -3738,6 +3768,35 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, } } =20 +/* MXU Instructions */ +static void gen_mxu(DisasContext *ctx, uint32_t opc) +{ + TCGv t0; + uint32_t xra, rb; + + t0 =3D tcg_temp_new(); + + switch (opc) { + case OPC_MXU_S32I2M: + xra =3D extract32(ctx->opcode, 6, 5); + rb =3D extract32(ctx->opcode, 16, 5); + + gen_load_gpr(t0, rb); + gen_store_mxu_gpr(t0, xra); + break; + + case OPC_MXU_S32M2I: + xra =3D extract32(ctx->opcode, 6, 5); + rb =3D extract32(ctx->opcode, 16, 5); + + gen_load_mxu_gpr(t0, xra); + gen_store_gpr(t0, rb); + break; + } + + tcg_temp_free(t0); +} + /* Godson integer instructions */ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) @@ -17818,6 +17877,12 @@ static void decode_opc_special2_legacy(CPUMIPSStat= e *env, DisasContext *ctx) check_insn(ctx, INSN_LOONGSON2F); gen_loongson_integer(ctx, op1, rd, rs, rt); break; + + case OPC_MXU_S32I2M: + case OPC_MXU_S32M2I: + gen_mxu(ctx, op1); + break; + case OPC_CLO: case OPC_CLZ: check_insn(ctx, ISA_MIPS32); @@ -20742,6 +20807,12 @@ void mips_tcg_init(void) fpu_fcr31 =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMIPSState, active_fpu.f= cr31), "fcr31"); + + for (i =3D 0; i < 16; i++) + mxu_gpr[i] =3D tcg_global_mem_new(cpu_env, + offsetof(CPUMIPSState, + active_tc.mxu_gpr[i]), + mxuregnames[i]); } =20 #include "translate_init.inc.c" --=20 2.18.0 From nobody Mon Feb 9 00:00:49 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@amazon.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153538085039624.10000614770422; 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X-IronPort-AV: E=Sophos;i="5.53,295,1531785600"; d="scan'208";a="694554219" To: qemu-devel@nongnu.org Date: Mon, 27 Aug 2018 10:38:02 -0400 Message-Id: <20180827143806.25048-3-jancraig@amazon.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180827143806.25048-1-jancraig@amazon.com> References: <20180827143806.25048-1-jancraig@amazon.com> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 72.21.196.25 Subject: [Qemu-devel] [PATCH v2 2/6] target/mips: Add MXU instruction S8LDD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds support for emulating the S8LDD MXU instruction. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - changed bitfield usage to extract32 - used deposit_tl instructions instead of shift and bitmask target/mips/translate.c | 62 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 60 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index ef819d67e0..f5725d8eda 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -365,6 +365,7 @@ enum { OPC_DCLZ =3D 0x24 | OPC_SPECIAL2, OPC_DCLO =3D 0x25 | OPC_SPECIAL2, /* MXU */ + OPC_MXU_S8LDD =3D 0x22 | OPC_SPECIAL2, OPC_MXU_S32I2M =3D 0x2F | OPC_SPECIAL2, OPC_MXU_S32M2I =3D 0x2E | OPC_SPECIAL2, /* Special */ @@ -3771,10 +3772,11 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, /* MXU Instructions */ static void gen_mxu(DisasContext *ctx, uint32_t opc) { - TCGv t0; - uint32_t xra, rb; + TCGv t0, t1; + uint32_t xra, rb, s8, optn3; =20 t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); =20 switch (opc) { case OPC_MXU_S32I2M: @@ -3792,9 +3794,64 @@ static void gen_mxu(DisasContext *ctx, uint32_t opc) gen_load_mxu_gpr(t0, xra); gen_store_gpr(t0, rb); break; + + case OPC_MXU_S8LDD: + xra =3D extract32(ctx->opcode, 6, 4); + s8 =3D extract32(ctx->opcode, 10, 8); + optn3 =3D extract32(ctx->opcode, 18, 3); + rb =3D extract32(ctx->opcode, 21, 5); + + gen_load_gpr(t0, rb); + tcg_gen_addi_tl(t0, t0, (int8_t)s8); + switch (optn3) { + case 0: /*XRa[7:0] =3D tmp8 */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, xra); + tcg_gen_deposit_tl(t0, t0, t1, 0, 8); + break; + case 1: /* XRa[15:8] =3D tmp8 */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, xra); + tcg_gen_deposit_tl(t0, t0, t1, 8, 8); + break; + case 2: /* XRa[23:16] =3D tmp8 */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, xra); + tcg_gen_deposit_tl(t0, t0, t1, 16, 8); + break; + case 3: /* XRa[31:24] =3D tmp8 */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, xra); + tcg_gen_deposit_tl(t0, t0, t1, 24, 8); + break; + case 4: /* XRa =3D {8'b0, tmp8, 8'b0, tmp8} */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_deposit_tl(t0, t1, t1, 16, 16); + break; + case 5: /* XRa =3D {tmp8, 8'b0, tmp8, 8'b0} */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_shli_tl(t1, t1, 8); + tcg_gen_deposit_tl(t0, t1, t1, 16, 16); + break; + case 6: /* XRa =3D {{8{sign of tmp8}}, tmp8, {8{sign of tmp8}}, tm= p8} */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_SB); + tcg_gen_mov_tl(t0, t1); + tcg_gen_andi_tl(t0, t0, 0xFF00FFFF); + tcg_gen_shli_tl(t1, t1, 16); + tcg_gen_or_tl(t0, t0, t1); + break; + case 7: /* XRa =3D {tmp8, tmp8, tmp8, tmp8} */ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_deposit_tl(t1, t1, t1, 8, 8); + tcg_gen_deposit_tl(t0, t1, t1, 16, 16); + break; + } + gen_store_mxu_gpr(t0, xra); + break; } =20 tcg_temp_free(t0); + tcg_temp_free(t1); } =20 /* Godson integer instructions */ @@ -17880,6 +17937,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) =20 case OPC_MXU_S32I2M: case OPC_MXU_S32M2I: + case OPC_MXU_S8LDD: gen_mxu(ctx, op1); break; =20 --=20 2.18.0 From nobody Mon Feb 9 00:00:49 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@amazon.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15353815697761020.0423966077648; Mon, 27 Aug 2018 07:52:49 -0700 (PDT) Received: from localhost ([::1]:53615 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fuIsq-00074w-Jh for importer@patchew.org; Mon, 27 Aug 2018 10:52:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45909) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fuIho-0005n1-6D for qemu-devel@nongnu.org; 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X-Received-From: 72.21.198.25 Subject: [Qemu-devel] [PATCH v2 3/6] target/mips: Add MXU instruction D16MUL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds support for emulating the D16MUL instruction. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - changed bitfield usage to extract32 - used sextract_tl instructions instead of shift and ext target/mips/translate.c | 51 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index f5725d8eda..8a6b4f2899 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -365,6 +365,7 @@ enum { OPC_DCLZ =3D 0x24 | OPC_SPECIAL2, OPC_DCLO =3D 0x25 | OPC_SPECIAL2, /* MXU */ + OPC_MXU_D16MUL =3D 0x08 | OPC_SPECIAL2, OPC_MXU_S8LDD =3D 0x22 | OPC_SPECIAL2, OPC_MXU_S32I2M =3D 0x2F | OPC_SPECIAL2, OPC_MXU_S32M2I =3D 0x2E | OPC_SPECIAL2, @@ -3772,11 +3773,13 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, /* MXU Instructions */ static void gen_mxu(DisasContext *ctx, uint32_t opc) { - TCGv t0, t1; - uint32_t xra, rb, s8, optn3; + TCGv t0, t1, t2, t3; + uint32_t rb, xra, xrb, xrc, xrd, s8, sel, optn2, optn3; =20 t0 =3D tcg_temp_new(); t1 =3D tcg_temp_new(); + t2 =3D tcg_temp_new(); + t3 =3D tcg_temp_new(); =20 switch (opc) { case OPC_MXU_S32I2M: @@ -3848,10 +3851,53 @@ static void gen_mxu(DisasContext *ctx, uint32_t opc) } gen_store_mxu_gpr(t0, xra); break; + + case OPC_MXU_D16MUL: + xra =3D extract32(ctx->opcode, 6, 4); + xrb =3D extract32(ctx->opcode, 10, 4); + xrc =3D extract32(ctx->opcode, 14, 4); + xrd =3D extract32(ctx->opcode, 18, 4); + optn2 =3D extract32(ctx->opcode, 22, 2); + sel =3D extract32(ctx->opcode, 24, 2); + + if (sel =3D=3D 1) { + /* D16MULE is not supported */ + generate_exception_end(ctx, EXCP_RI); + } + gen_load_mxu_gpr(t1, xrb); + tcg_gen_sextract_tl(t0, t1, 0, 16); + tcg_gen_sextract_tl(t1, t1, 16, 16); + gen_load_mxu_gpr(t3, xrc); + tcg_gen_sextract_tl(t2, t3, 0, 16); + tcg_gen_sextract_tl(t3, t3, 16, 16); + + switch (optn2) { + case 0: /* XRB.H*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case 1: /* XRB.L*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case 2: /* XRB.H*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + case 3: /* XRB.L*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + } + gen_store_mxu_gpr(t3, xra); + gen_store_mxu_gpr(t2, xrd); + break; } =20 tcg_temp_free(t0); tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); } =20 /* Godson integer instructions */ @@ -17938,6 +17984,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) case OPC_MXU_S32I2M: case OPC_MXU_S32M2I: case OPC_MXU_S8LDD: + case OPC_MXU_D16MUL: gen_mxu(ctx, op1); break; =20 --=20 2.18.0 From nobody Mon Feb 9 00:00:49 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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X-Received-From: 207.171.190.10 Subject: [Qemu-devel] [PATCH v2 4/6] target/mips: Add MXU instruction D16MAC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds support for emulating the D16MAC instruction. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - changed bitfield usage to extract32 - used sextract_tl instructions instead of shift and ext target/mips/translate.c | 62 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 8a6b4f2899..7d37567652 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -366,6 +366,7 @@ enum { OPC_DCLO =3D 0x25 | OPC_SPECIAL2, /* MXU */ OPC_MXU_D16MUL =3D 0x08 | OPC_SPECIAL2, + OPC_MXU_D16MAC =3D 0x0A | OPC_SPECIAL2, OPC_MXU_S8LDD =3D 0x22 | OPC_SPECIAL2, OPC_MXU_S32I2M =3D 0x2F | OPC_SPECIAL2, OPC_MXU_S32M2I =3D 0x2E | OPC_SPECIAL2, @@ -3774,7 +3775,7 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, static void gen_mxu(DisasContext *ctx, uint32_t opc) { TCGv t0, t1, t2, t3; - uint32_t rb, xra, xrb, xrc, xrd, s8, sel, optn2, optn3; + uint32_t rb, xra, xrb, xrc, xrd, s8, sel, optn2, optn3, aptn2; =20 t0 =3D tcg_temp_new(); t1 =3D tcg_temp_new(); @@ -3892,6 +3893,64 @@ static void gen_mxu(DisasContext *ctx, uint32_t opc) gen_store_mxu_gpr(t3, xra); gen_store_mxu_gpr(t2, xrd); break; + + case OPC_MXU_D16MAC: + xra =3D extract32(ctx->opcode, 6, 4); + xrb =3D extract32(ctx->opcode, 10, 4); + xrc =3D extract32(ctx->opcode, 14, 4); + xrd =3D extract32(ctx->opcode, 18, 4); + optn2 =3D extract32(ctx->opcode, 22, 2); + aptn2 =3D extract32(ctx->opcode, 24, 2); + + gen_load_mxu_gpr(t1, xrb); + tcg_gen_sextract_tl(t0, t1, 0, 16); + tcg_gen_sextract_tl(t1, t1, 16, 16); + gen_load_mxu_gpr(t3, xrc); + tcg_gen_sextract_tl(t2, t3, 0, 16); + tcg_gen_sextract_tl(t3, t3, 16, 16); + + switch (optn2) { + case 0: /* XRB.H*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case 1: /* XRB.L*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case 2: /* XRB.H*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + case 3: /* XRB.L*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + } + gen_load_mxu_gpr(t0, xra); + gen_load_mxu_gpr(t1, xrd); + + switch (aptn2) { + case 0: + tcg_gen_add_tl(t3, t0, t3); + tcg_gen_add_tl(t2, t1, t2); + break; + case 1: + tcg_gen_add_tl(t3, t0, t3); + tcg_gen_sub_tl(t2, t1, t2); + break; + case 2: + tcg_gen_sub_tl(t3, t0, t3); + tcg_gen_add_tl(t2, t1, t2); + break; + case 3: + tcg_gen_sub_tl(t3, t0, t3); + tcg_gen_sub_tl(t2, t1, t2); + break; + } + gen_store_mxu_gpr(t3, xra); + gen_store_mxu_gpr(t2, xrd); + break; } =20 tcg_temp_free(t0); @@ -17985,6 +18044,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) case OPC_MXU_S32M2I: case OPC_MXU_S8LDD: case OPC_MXU_D16MUL: + case OPC_MXU_D16MAC: gen_mxu(ctx, op1); break; =20 --=20 2.18.0 From nobody Mon Feb 9 00:00:49 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 72.21.198.25 Subject: [Qemu-devel] [PATCH v2 5/6] target/mips: Add MXU instructions Q8MUL and Q8MULSU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds support for emulating the Q8MUL and Q8MULSU instructions. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - changed bitfield usage to extract32 target/mips/translate.c | 70 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 69 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 7d37567652..e2def36b03 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -370,6 +370,7 @@ enum { OPC_MXU_S8LDD =3D 0x22 | OPC_SPECIAL2, OPC_MXU_S32I2M =3D 0x2F | OPC_SPECIAL2, OPC_MXU_S32M2I =3D 0x2E | OPC_SPECIAL2, + OPC_MXU_Q8MUL =3D 0x38 | OPC_SPECIAL2, /* Special */ OPC_SDBBP =3D 0x3F | OPC_SPECIAL2, }; @@ -3774,13 +3775,17 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, /* MXU Instructions */ static void gen_mxu(DisasContext *ctx, uint32_t opc) { - TCGv t0, t1, t2, t3; + TCGv t0, t1, t2, t3, t4, t5, t6, t7; uint32_t rb, xra, xrb, xrc, xrd, s8, sel, optn2, optn3, aptn2; =20 t0 =3D tcg_temp_new(); t1 =3D tcg_temp_new(); t2 =3D tcg_temp_new(); t3 =3D tcg_temp_new(); + t4 =3D tcg_temp_new(); + t5 =3D tcg_temp_new(); + t6 =3D tcg_temp_new(); + t7 =3D tcg_temp_new(); =20 switch (opc) { case OPC_MXU_S32I2M: @@ -3951,12 +3956,74 @@ static void gen_mxu(DisasContext *ctx, uint32_t opc) gen_store_mxu_gpr(t3, xra); gen_store_mxu_gpr(t2, xrd); break; + + case OPC_MXU_Q8MUL: + xra =3D extract32(ctx->opcode, 6, 4); + xrb =3D extract32(ctx->opcode, 10, 4); + xrc =3D extract32(ctx->opcode, 14, 4); + xrd =3D extract32(ctx->opcode, 18, 4); + sel =3D extract32(ctx->opcode, 22, 4); + + gen_load_mxu_gpr(t3, xrb); + gen_load_mxu_gpr(t7, xrc); + + if (sel =3D=3D 0x2) { + /* Q8MULSU */ + tcg_gen_ext8s_tl(t0, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t1, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t2, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t3, t3); + } else { + /* Q8MUL */ + tcg_gen_ext8u_tl(t0, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t1, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t2, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t3, t3); + } + + tcg_gen_ext8u_tl(t4, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t5, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t6, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t7, t7); + + tcg_gen_mul_tl(t0, t0, t4); + tcg_gen_mul_tl(t1, t1, t5); + tcg_gen_mul_tl(t2, t2, t6); + tcg_gen_mul_tl(t3, t3, t7); + + tcg_gen_andi_tl(t0, t0, 0xFFFF); + tcg_gen_andi_tl(t1, t1, 0xFFFF); + tcg_gen_andi_tl(t2, t2, 0xFFFF); + tcg_gen_andi_tl(t3, t3, 0xFFFF); + + tcg_gen_shli_tl(t1, t1, 16); + tcg_gen_shli_tl(t3, t3, 16); + + tcg_gen_or_tl(t0, t0, t1); + tcg_gen_or_tl(t1, t2, t3); + + gen_store_mxu_gpr(t0, xrd); + gen_store_mxu_gpr(t1, xra); + break; } =20 tcg_temp_free(t0); tcg_temp_free(t1); tcg_temp_free(t2); tcg_temp_free(t3); + tcg_temp_free(t4); + tcg_temp_free(t5); + tcg_temp_free(t6); + tcg_temp_free(t7); } =20 /* Godson integer instructions */ @@ -18045,6 +18112,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) case OPC_MXU_S8LDD: case OPC_MXU_D16MUL: case OPC_MXU_D16MAC: + case OPC_MXU_Q8MUL: gen_mxu(ctx, op1); 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X-Received-From: 72.21.196.25 Subject: [Qemu-devel] [PATCH v2 6/6] target/mips: Add MXU instructions S32LDD and S32LDDR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Janeczek via Qemu-devel Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds support for emulating the S32LDD and S32LDDR MXU instructions. Signed-off-by: Craig Janeczek --- v1 - initial patch v2 - changed bitfield usage to extract32 target/mips/translate.c | 43 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 38 insertions(+), 5 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index e2def36b03..2eb7c02741 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -347,7 +347,8 @@ enum { OPC_MSUB =3D 0x04 | OPC_SPECIAL2, OPC_MSUBU =3D 0x05 | OPC_SPECIAL2, /* Loongson 2F */ - OPC_MULT_G_2F =3D 0x10 | OPC_SPECIAL2, + /* opcode 0x10 overlaps loongson and MXU command */ + OPC_MULT_G_2F_MXU_S32LDD =3D 0x10 | OPC_SPECIAL2, OPC_DMULT_G_2F =3D 0x11 | OPC_SPECIAL2, OPC_MULTU_G_2F =3D 0x12 | OPC_SPECIAL2, OPC_DMULTU_G_2F =3D 0x13 | OPC_SPECIAL2, @@ -3776,7 +3777,7 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, static void gen_mxu(DisasContext *ctx, uint32_t opc) { TCGv t0, t1, t2, t3, t4, t5, t6, t7; - uint32_t rb, xra, xrb, xrc, xrd, s8, sel, optn2, optn3, aptn2; + uint32_t rb, xra, xrb, xrc, xrd, s8, s12, sel, optn2, optn3, aptn2; =20 t0 =3D tcg_temp_new(); t1 =3D tcg_temp_new(); @@ -3858,6 +3859,29 @@ static void gen_mxu(DisasContext *ctx, uint32_t opc) gen_store_mxu_gpr(t0, xra); break; =20 + case OPC_MULT_G_2F_MXU_S32LDD: + xra =3D extract32(ctx->opcode, 6, 4); + s12 =3D extract32(ctx->opcode, 10, 10); + sel =3D extract32(ctx->opcode, 20, 1); + rb =3D extract32(ctx->opcode, 21, 5); + + gen_load_gpr(t0, rb); + + tcg_gen_movi_tl(t1, s12); + tcg_gen_shli_tl(t1, t1, 2); + if (s12 & 0x200) { + tcg_gen_ori_tl(t1, t1, 0xFFFFF000); + } + tcg_gen_add_tl(t1, t0, t1); + tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_SL); + + if (sel =3D=3D 1) { + /* S32LDDR */ + tcg_gen_bswap32_tl(t1, t1); + } + gen_store_mxu_gpr(t1, xra); + break; + case OPC_MXU_D16MUL: xra =3D extract32(ctx->opcode, 6, 4); xrb =3D extract32(ctx->opcode, 10, 4); @@ -4039,7 +4063,7 @@ static void gen_loongson_integer(DisasContext *ctx, u= int32_t opc, =20 switch (opc) { case OPC_MULT_G_2E: - case OPC_MULT_G_2F: + case OPC_MULT_G_2F_MXU_S32LDD: case OPC_MULTU_G_2E: case OPC_MULTU_G_2F: #if defined(TARGET_MIPS64) @@ -4062,7 +4086,7 @@ static void gen_loongson_integer(DisasContext *ctx, u= int32_t opc, =20 switch (opc) { case OPC_MULT_G_2E: - case OPC_MULT_G_2F: + case OPC_MULT_G_2F_MXU_S32LDD: tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); break; @@ -18099,7 +18123,6 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) break; case OPC_DIV_G_2F: case OPC_DIVU_G_2F: - case OPC_MULT_G_2F: case OPC_MULTU_G_2F: case OPC_MOD_G_2F: case OPC_MODU_G_2F: @@ -18116,6 +18139,16 @@ static void decode_opc_special2_legacy(CPUMIPSStat= e *env, DisasContext *ctx) gen_mxu(ctx, op1); break; =20 + case OPC_MULT_G_2F_MXU_S32LDD: + /* There is an overlap of opcodes between Loongson2F and MXU */ + if (ctx->insn_flags & INSN_LOONGSON2F) { + check_insn(ctx, INSN_LOONGSON2F); + gen_loongson_integer(ctx, op1, rd, rs, rt); + } else { + gen_mxu(ctx, op1); + } + break; + case OPC_CLO: case OPC_CLZ: check_insn(ctx, ISA_MIPS32); --=20 2.18.0