From nobody Wed Nov 5 16:18:28 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153535071207767.85805005658722; Sun, 26 Aug 2018 23:18:32 -0700 (PDT) Received: from localhost ([::1]:51570 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fuAr8-0002yA-Ti for importer@patchew.org; Mon, 27 Aug 2018 02:18:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50703) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fuAnA-0007bE-P6 for qemu-devel@nongnu.org; Mon, 27 Aug 2018 02:14:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fuAgm-0002wt-2e for qemu-devel@nongnu.org; Mon, 27 Aug 2018 02:07:50 -0400 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:51758 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fuAgl-0002wW-QC for qemu-devel@nongnu.org; Mon, 27 Aug 2018 02:07:47 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7CD0240201BE for ; Mon, 27 Aug 2018 06:07:47 +0000 (UTC) Received: from blackfin.pond.sub.org (ovpn-116-97.ams2.redhat.com [10.36.116.97]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5C79D10075D4; Mon, 27 Aug 2018 06:07:45 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 2F9E7113860E; Mon, 27 Aug 2018 08:07:44 +0200 (CEST) From: Markus Armbruster To: qemu-devel@nongnu.org Date: Mon, 27 Aug 2018 08:07:44 +0200 Message-Id: <20180827060744.13770-4-armbru@redhat.com> In-Reply-To: <20180827060744.13770-1-armbru@redhat.com> References: <20180827060744.13770-1-armbru@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.6]); Mon, 27 Aug 2018 06:07:47 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.6]); Mon, 27 Aug 2018 06:07:47 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'armbru@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [PULL 3/3] intel-iommu: replace more vtd_err_* traces X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Peter Xu Replace all the trace_vtd_err_*() hooks with the new error_report_once() since they are similar to trace_vtd_err() - dumping the first error would be mostly enough, then we have them on by default too. Signed-off-by: Peter Xu Message-Id: <20180815095328.32414-4-peterx@redhat.com> Signed-off-by: Markus Armbruster --- hw/i386/intel_iommu.c | 63 ++++++++++++++++++++++++++++++------------- hw/i386/trace-events | 12 --------- 2 files changed, 45 insertions(+), 30 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index ed66ca78f5..9e4e7ed3bb 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -705,7 +705,8 @@ static int vtd_iova_to_slpte(VTDContextEntry *ce, uint6= 4_t iova, bool is_write, uint64_t access_right_check; =20 if (!vtd_iova_range_check(iova, ce, aw_bits)) { - trace_vtd_err_dmar_iova_overflow(iova); + error_report_once("%s: detected IOVA overflow (iova=3D0x%"PRIx64")= ", + __func__, iova); return -VTD_FR_ADDR_BEYOND_MGAW; } =20 @@ -717,7 +718,8 @@ static int vtd_iova_to_slpte(VTDContextEntry *ce, uint6= 4_t iova, bool is_write, slpte =3D vtd_get_slpte(addr, offset); =20 if (slpte =3D=3D (uint64_t)-1) { - trace_vtd_err_dmar_slpte_read_error(iova, level); + error_report_once("%s: detected read error on DMAR slpte " + "(iova=3D0x%"PRIx64")", __func__, iova); if (level =3D=3D vtd_ce_get_level(ce)) { /* Invalid programming of context-entry */ return -VTD_FR_CONTEXT_ENTRY_INV; @@ -728,11 +730,17 @@ static int vtd_iova_to_slpte(VTDContextEntry *ce, uin= t64_t iova, bool is_write, *reads =3D (*reads) && (slpte & VTD_SL_R); *writes =3D (*writes) && (slpte & VTD_SL_W); if (!(slpte & access_right_check)) { - trace_vtd_err_dmar_slpte_perm_error(iova, level, slpte, is_wri= te); + error_report_once("%s: detected slpte permission error " + "(iova=3D0x%"PRIx64", level=3D0x%"PRIx32", " + "slpte=3D0x%"PRIx64", write=3D%d)", __func__, + iova, level, slpte, is_write); return is_write ? -VTD_FR_WRITE : -VTD_FR_READ; } if (vtd_slpte_nonzero_rsvd(slpte, level)) { - trace_vtd_err_dmar_slpte_resv_error(iova, level, slpte); + error_report_once("%s: detected splte reserve non-zero " + "iova=3D0x%"PRIx64", level=3D0x%"PRIx32 + "slpte=3D0x%"PRIx64")", __func__, iova, + level, slpte); return -VTD_FR_PAGING_ENTRY_RSVD; } =20 @@ -1696,7 +1704,10 @@ static void vtd_handle_gcmd_qie(IntelIOMMUState *s, = bool en) /* Ok - report back to driver */ vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_QIES, 0); } else { - trace_vtd_err_qi_disable(s->iq_head, s->iq_tail, s->iq_last_de= sc_type); + error_report_once("%s: detected improper state when disable QI= " + "(head=3D0x%"PRIx16", tail=3D0x%"PRIx16", " + "last_type=3D%d)", __func__, s->iq_head, + s->iq_tail, s->iq_last_desc_type); } } } @@ -2093,7 +2104,9 @@ static void vtd_fetch_inv_desc(IntelIOMMUState *s) =20 if (s->iq_tail >=3D s->iq_size) { /* Detects an invalid Tail pointer */ - trace_vtd_err_qi_tail(s->iq_tail, s->iq_size); + error_report_once("%s: detected invalid QI tail " + "(tail=3D0x%"PRIx16", size=3D0x%"PRIx16")", + __func__, s->iq_tail, s->iq_size); vtd_handle_inv_queue_error(s); return; } @@ -2506,10 +2519,12 @@ static IOMMUTLBEntry vtd_iommu_translate(IOMMUMemor= yRegion *iommu, hwaddr addr, iotlb.iova, iotlb.translated_addr, iotlb.addr_mask); } else { - trace_vtd_err_dmar_translate(pci_bus_num(vtd_as->bus), - VTD_PCI_SLOT(vtd_as->devfn), - VTD_PCI_FUNC(vtd_as->devfn), - iotlb.iova); + error_report_once("%s: detected translation failure " + "(dev=3D%02x:%02x:%02x, iova=3D0x%"PRIx64")", + __func__, pci_bus_num(vtd_as->bus), + VTD_PCI_SLOT(vtd_as->devfn), + VTD_PCI_FUNC(vtd_as->devfn), + iotlb.iova); } =20 return iotlb; @@ -2625,15 +2640,19 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uin= t16_t index, le64_to_cpu(entry->data[0])); =20 if (!entry->irte.present) { - trace_vtd_err_irte(index, le64_to_cpu(entry->data[1]), - le64_to_cpu(entry->data[0])); + error_report_once("%s: detected non-present IRTE " + "(index=3D%u, high=3D0x%"PRIx64", low=3D0x%"PRIx= 64")", + __func__, index, le64_to_cpu(entry->data[1]), + le64_to_cpu(entry->data[0])); return -VTD_FR_IR_ENTRY_P; } =20 if (entry->irte.__reserved_0 || entry->irte.__reserved_1 || entry->irte.__reserved_2) { - trace_vtd_err_irte(index, le64_to_cpu(entry->data[1]), - le64_to_cpu(entry->data[0])); + error_report_once("%s: detected non-zero reserved IRTE " + "(index=3D%u, high=3D0x%"PRIx64", low=3D0x%"PRIx= 64")", + __func__, index, le64_to_cpu(entry->data[1]), + le64_to_cpu(entry->data[0])); return -VTD_FR_IR_IRTE_RSVD; } =20 @@ -2647,7 +2666,9 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint1= 6_t index, case VTD_SVT_ALL: mask =3D vtd_svt_mask[entry->irte.sid_q]; if ((source_id & mask) !=3D (sid & mask)) { - trace_vtd_err_irte_sid(index, sid, source_id); + error_report_once("%s: invalid IRTE SID " + "(index=3D%u, sid=3D%u, source_id=3D%u)", + __func__, index, sid, source_id); return -VTD_FR_IR_SID_ERR; } break; @@ -2657,13 +2678,17 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uin= t16_t index, bus_min =3D source_id & 0xff; bus =3D sid >> 8; if (bus > bus_max || bus < bus_min) { - trace_vtd_err_irte_sid_bus(index, bus, bus_min, bus_max); + error_report_once("%s: invalid SVT_BUS " + "(index=3D%u, bus=3D%u, min=3D%u, max=3D= %u)", + __func__, index, bus, bus_min, bus_max); return -VTD_FR_IR_SID_ERR; } break; =20 default: - trace_vtd_err_irte_svt(index, entry->irte.sid_vtype); + error_report_once("%s: detected invalid IRTE SVT " + "(index=3D%u, type=3D%d)", __func__, + index, entry->irte.sid_vtype); /* Take this as verification failure. */ return -VTD_FR_IR_SID_ERR; break; @@ -2785,7 +2810,9 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState *i= ommu, if (addr.addr.sub_valid) { trace_vtd_ir_remap_type("MSI"); if (origin->data & VTD_IR_MSI_DATA_RESERVED) { - trace_vtd_err_ir_msi_invalid(sid, origin->address, origin->dat= a); + error_report_once("%s: invalid IR MSI " + "(sid=3D%u, address=3D0x%"PRIx64", data=3D0x= %"PRIx32")", + __func__, sid, origin->address, origin->data= ); return -VTD_FR_IR_REQ_RSVD; } } else { diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 922431b1bb..9e6fc4dca9 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -69,19 +69,7 @@ vtd_ir_remap_msi_req(uint64_t addr, uint64_t data) "addr= 0x%"PRIx64" data 0x%"PR vtd_fsts_ppf(bool set) "FSTS PPF bit set to %d" vtd_fsts_clear_ip(void) "" vtd_frr_new(int index, uint64_t hi, uint64_t lo) "index %d high 0x%"PRIx64= " low 0x%"PRIx64 -vtd_err_dmar_iova_overflow(uint64_t iova) "iova 0x%"PRIx64 -vtd_err_dmar_slpte_read_error(uint64_t iova, int level) "iova 0x%"PRIx64" = level %d" -vtd_err_dmar_slpte_perm_error(uint64_t iova, int level, uint64_t slpte, bo= ol is_write) "iova 0x%"PRIx64" level %d slpte 0x%"PRIx64" write %d" -vtd_err_dmar_slpte_resv_error(uint64_t iova, int level, uint64_t slpte) "i= ova 0x%"PRIx64" level %d slpte 0x%"PRIx64 -vtd_err_dmar_translate(uint8_t bus, uint8_t slot, uint8_t func, uint64_t i= ova) "dev %02x:%02x.%02x iova 0x%"PRIx64 vtd_warn_invalid_qi_tail(uint16_t tail) "tail 0x%"PRIx16 -vtd_err_qi_disable(uint16_t head, uint16_t tail, int type) "head 0x%"PRIx1= 6" tail 0x%"PRIx16" last_desc_type %d" -vtd_err_qi_tail(uint16_t tail, uint16_t size) "tail 0x%"PRIx16" size 0x%"P= RIx16 -vtd_err_irte(int index, uint64_t lo, uint64_t hi) "index %d low 0x%"PRIx64= " high 0x%"PRIx64 -vtd_err_irte_sid(int index, uint16_t req, uint16_t target) "index %d SVT_A= LL sid 0x%"PRIx16" (should be: 0x%"PRIx16")" -vtd_err_irte_sid_bus(int index, uint8_t bus, uint8_t min, uint8_t max) "in= dex %d SVT_BUS bus 0x%"PRIx8" (should be: 0x%"PRIx8"-0x%"PRIx8")" -vtd_err_irte_svt(int index, int type) "index %d SVT type %d" -vtd_err_ir_msi_invalid(uint16_t sid, uint64_t addr, uint64_t data) "sid 0x= %"PRIx16" addr 0x%"PRIx64" data 0x%"PRIx64 vtd_warn_ir_vector(uint16_t sid, int index, int vec, int target) "sid 0x%"= PRIx16" index %d vec %d (should be: %d)" vtd_warn_ir_trigger(uint16_t sid, int index, int trig, int target) "sid 0x= %"PRIx16" index %d trigger %d (should be: %d)" =20 --=20 2.17.1