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[50.200.230.211]) by smtp.gmail.com with ESMTPSA id p3-v6sm9913916pfo.130.2018.08.24.07.14.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 24 Aug 2018 07:14:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=L7daPktJf66RIlptMUtJCq/HpZB2ABcq2rEcvJuDG8c=; b=ItH69KHzdGR/MRQhElncDMstrmux4YWaMUdC6Eml3MeSTsOZgGVi1JhFj5BfR0S615 8o6R/9DG1tR4Lxsi2P3DolFUbzeUJP2PFgK4UQty96vaK3IzMApdOa8WlO/jypiIWzg9 N0Y4YvC7fBQ0dbqjCpoN9Pr7MsWd2Naow3Fm0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=L7daPktJf66RIlptMUtJCq/HpZB2ABcq2rEcvJuDG8c=; b=LASuaSdG1B81EhBjrI7PcB6BqZ0sexbAbq2ofJ0VuLm8lqKHyzysx2N1YRCO0IkneO tW09SCQZ9iVkUNG7fi9TtyfmxcqmFE2mS6HDal3g+rt/5v8NIvcv1MDskdqsmgzrsYd7 eKBSI5ASKDfldHi6TF82AGZmC8DAbEHh26ZDDpq6O2u9doKY1tTClQMU16k5ysvj8Iyh OMYdAxTQhw/FcdnRZ0vV6EKfHVAv1JJg351yVBUgOVfLfr2ngJhPkydjM8Hgxx7lEdad AexUO9jQbakwd+sd2fVK8JMLBROTqrcDZbdWYvoF3GgAcbB0KhijND1r8cOSg0ll+k/X ge4g== X-Gm-Message-State: APzg51CovHZ+51uAJW2MldA9VSTr2D93nDkWL7KpWvqYKkkwJU6ZZIYM QYc+1kNOTX6tYIKwbM9QcNnxo3+516Q= X-Google-Smtp-Source: ANB0VdYZ2dPWlJm0yPYyS7Mdn8wcLgmK2L8aQwBTYh1YMIN3MZvBsJvFATxFEPcO2TB4L+2ipYKSig== X-Received: by 2002:a17:902:b40c:: with SMTP id x12-v6mr1908099plr.163.1535120070668; Fri, 24 Aug 2018 07:14:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 24 Aug 2018 07:14:28 -0700 Message-Id: <20180824141428.27268-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH] target/arm: Fix cpu_get_tb_cpu_flags vs !sve X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Not only are the sve-related tb_flags fields unused when SVE is disabled, but not all of the cpu registers are initialized properly for computing same. This can corrupt other fields by oring in -1. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 45 ++++++++++++++++++++++++--------------------- 1 file changed, 24 insertions(+), 21 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 088f452716..64b1564594 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12587,36 +12587,39 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, uint32_t flags; =20 if (is_a64(env)) { - int sve_el =3D sve_exception_el(env); - uint32_t zcr_len; - *pc =3D env->pc; flags =3D ARM_TBFLAG_AARCH64_STATE_MASK; /* Get control bits for tagged addresses */ flags |=3D (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT= ); flags |=3D (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT= ); - flags |=3D sve_el << ARM_TBFLAG_SVEEXC_EL_SHIFT; =20 - /* If SVE is disabled, but FP is enabled, - then the effective len is 0. */ - if (sve_el !=3D 0 && fp_el =3D=3D 0) { - zcr_len =3D 0; - } else { - int current_el =3D arm_current_el(env); - ARMCPU *cpu =3D arm_env_get_cpu(env); + if (arm_feature(env, ARM_FEATURE_SVE)) { + int sve_el =3D sve_exception_el(env); + uint32_t zcr_len; =20 - zcr_len =3D cpu->sve_max_vq - 1; - if (current_el <=3D 1) { - zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1= ]); - } - if (current_el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { - zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2= ]); - } - if (current_el < 3 && arm_feature(env, ARM_FEATURE_EL3)) { - zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3= ]); + /* If SVE is disabled, but FP is enabled, + * then the effective len is 0. + */ + if (sve_el !=3D 0 && fp_el =3D=3D 0) { + zcr_len =3D 0; + } else { + int current_el =3D arm_current_el(env); + ARMCPU *cpu =3D arm_env_get_cpu(env); + + zcr_len =3D cpu->sve_max_vq - 1; + if (current_el <=3D 1) { + zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_= el[1]); + } + if (current_el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { + zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_= el[2]); + } + if (current_el < 3 && arm_feature(env, ARM_FEATURE_EL3)) { + zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_= el[3]); + } } + flags |=3D sve_el << ARM_TBFLAG_SVEEXC_EL_SHIFT; + flags |=3D zcr_len << ARM_TBFLAG_ZCR_LEN_SHIFT; } - flags |=3D zcr_len << ARM_TBFLAG_ZCR_LEN_SHIFT; } else { *pc =3D env->regs[15]; flags =3D (env->thumb << ARM_TBFLAG_THUMB_SHIFT) --=20 2.17.1