From nobody Tue Apr 15 15:44:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15351053951331014.5637334595364; Fri, 24 Aug 2018 03:09:55 -0700 (PDT) Received: from localhost ([::1]:40848 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ft92P-0000XJ-Ri for importer@patchew.org; Fri, 24 Aug 2018 06:09:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35720) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ft8UE-0007aQ-Ku for qemu-devel@nongnu.org; Fri, 24 Aug 2018 05:34:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ft8UD-0004k2-0H for qemu-devel@nongnu.org; Fri, 24 Aug 2018 05:34:34 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44896) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ft8UB-0004eK-1e for qemu-devel@nongnu.org; Fri, 24 Aug 2018 05:34:31 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ft8U9-0006c6-Hh for qemu-devel@nongnu.org; Fri, 24 Aug 2018 10:34:29 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 24 Aug 2018 10:33:29 +0100 Message-Id: <20180824093343.11346-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180824093343.11346-1-peter.maydell@linaro.org> References: <20180824093343.11346-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 38/52] hw/ssi/pl022: Correct wrong DMACR and ICR handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In the PL022, register offset 0x20 is the ICR, a write-only interrupt-clear register. Register offset 0x24 is DMACR, the DMA control register. We were incorrectly implementing (a stub version of) DMACR at 0x20, and not implementing anything at 0x24. Fix this bug. Signed-off-by: Peter Maydell Message-id: 20180820141116.9118-21-peter.maydell@linaro.org Reviewed-by: Richard Henderson --- hw/ssi/pl022.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/ssi/pl022.c b/hw/ssi/pl022.c index d310671d18e..e58247554cc 100644 --- a/hw/ssi/pl022.c +++ b/hw/ssi/pl022.c @@ -146,7 +146,7 @@ static uint64_t pl022_read(void *opaque, hwaddr offset, return s->is; case 0x1c: /* MIS */ return s->im & s->is; - case 0x20: /* DMACR */ + case 0x24: /* DMACR */ /* Not implemented. */ return 0; default: @@ -192,7 +192,15 @@ static void pl022_write(void *opaque, hwaddr offset, s->im =3D value; pl022_update(s); break; - case 0x20: /* DMACR */ + case 0x20: /* ICR */ + /* + * write-1-to-clear: bit 0 clears ROR, bit 1 clears RT; + * RX and TX interrupts cannot be cleared this way. + */ + value &=3D PL022_INT_ROR | PL022_INT_RT; + s->is &=3D ~value; + break; + case 0x24: /* DMACR */ if (value) { qemu_log_mask(LOG_UNIMP, "pl022: DMA not implemented\n"); } --=20 2.18.0