From nobody Tue Apr 15 15:44:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535104789116230.0174811776751; Fri, 24 Aug 2018 02:59:49 -0700 (PDT) Received: from localhost ([::1]:40781 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ft8se-0007Jt-0N for importer@patchew.org; Fri, 24 Aug 2018 05:59:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35466) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ft8To-0007EO-GL for qemu-devel@nongnu.org; Fri, 24 Aug 2018 05:34:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ft8Tn-0003hq-Kw for qemu-devel@nongnu.org; Fri, 24 Aug 2018 05:34:08 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44876) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ft8Tn-0003ee-Bp for qemu-devel@nongnu.org; Fri, 24 Aug 2018 05:34:07 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ft8Tm-0006Sx-9U for qemu-devel@nongnu.org; Fri, 24 Aug 2018 10:34:06 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 24 Aug 2018 10:33:08 +0100 Message-Id: <20180824093343.11346-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180824093343.11346-1-peter.maydell@linaro.org> References: <20180824093343.11346-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 17/52] target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" On 32-bit exception entry, CPSR.J must always be set to 0 (see v7A Arm ARM DDI0406C.c B1.8.5). CPSR.IL must also be cleared on 32-bit exception entry (see v8A Arm ARM DDI0487C.a G1.10). Clear these bits. (This fixes a bug which will never be noticed by non-buggy guests.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Reviewed-by: Luc Michel Message-id: 20180820153020.21478-6-peter.maydell@linaro.org --- target/arm/helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 10f40b01700..b0ab18af43e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8054,6 +8054,8 @@ static void take_aarch32_exception(CPUARMState *env, = int new_mode, if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { env->uncached_cpsr |=3D CPSR_E; } + /* J and IL must always be cleared for exception entry */ + env->uncached_cpsr &=3D ~(CPSR_IL | CPSR_J); env->daif |=3D mask; =20 if (new_mode =3D=3D ARM_CPU_MODE_HYP) { --=20 2.18.0