From nobody Tue Apr 15 14:50:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535104612035174.54034793738538; Fri, 24 Aug 2018 02:56:52 -0700 (PDT) Received: from localhost ([::1]:40769 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ft8pm-00052m-Jb for importer@patchew.org; Fri, 24 Aug 2018 05:56:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35457) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ft8Tn-0007DX-Se for qemu-devel@nongnu.org; Fri, 24 Aug 2018 05:34:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ft8Tm-0003ew-Mx for qemu-devel@nongnu.org; Fri, 24 Aug 2018 05:34:07 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44874) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ft8Tm-0003ZB-D4 for qemu-devel@nongnu.org; Fri, 24 Aug 2018 05:34:06 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ft8Tl-0006SU-Bm for qemu-devel@nongnu.org; Fri, 24 Aug 2018 10:34:05 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 24 Aug 2018 10:33:07 +0100 Message-Id: <20180824093343.11346-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180824093343.11346-1-peter.maydell@linaro.org> References: <20180824093343.11346-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 16/52] target/arm: Implement support for taking exceptions to Hyp mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement the necessary support code for taking exceptions to Hyp mode in AArch32. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Reviewed-by: Luc Michel Message-id: 20180820153020.21478-5-peter.maydell@linaro.org --- target/arm/helper.c | 82 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index b47657c31b2..10f40b01700 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8073,6 +8073,83 @@ static void take_aarch32_exception(CPUARMState *env,= int new_mode, env->regs[15] =3D newpc; } =20 +static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) +{ + /* + * Handle exception entry to Hyp mode; this is sufficiently + * different to entry to other AArch32 modes that we handle it + * separately here. + * + * The vector table entry used is always the 0x14 Hyp mode entry point, + * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp. + * The offset applied to the preferred return address is always zero + * (see DDI0487C.a section G1.12.3). + * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. + */ + uint32_t addr, mask; + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (cs->exception_index) { + case EXCP_UDEF: + addr =3D 0x04; + break; + case EXCP_SWI: + addr =3D 0x14; + break; + case EXCP_BKPT: + /* Fall through to prefetch abort. */ + case EXCP_PREFETCH_ABORT: + env->cp15.ifar_s =3D env->exception.vaddress; + qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n", + (uint32_t)env->exception.vaddress); + addr =3D 0x0c; + break; + case EXCP_DATA_ABORT: + env->cp15.dfar_s =3D env->exception.vaddress; + qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n", + (uint32_t)env->exception.vaddress); + addr =3D 0x10; + break; + case EXCP_IRQ: + addr =3D 0x18; + break; + case EXCP_FIQ: + addr =3D 0x1c; + break; + case EXCP_HVC: + addr =3D 0x08; + break; + case EXCP_HYP_TRAP: + addr =3D 0x14; + default: + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); + } + + if (cs->exception_index !=3D EXCP_IRQ && cs->exception_index !=3D EXCP= _FIQ) { + env->cp15.esr_el[2] =3D env->exception.syndrome; + } + + if (arm_current_el(env) !=3D 2 && addr < 0x14) { + addr =3D 0x14; + } + + mask =3D 0; + if (!(env->cp15.scr_el3 & SCR_EA)) { + mask |=3D CPSR_A; + } + if (!(env->cp15.scr_el3 & SCR_IRQ)) { + mask |=3D CPSR_I; + } + if (!(env->cp15.scr_el3 & SCR_FIQ)) { + mask |=3D CPSR_F; + } + + addr +=3D env->cp15.hvbar; + + take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr); +} + static void arm_cpu_do_interrupt_aarch32(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -8108,6 +8185,11 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *c= s) env->cp15.mdscr_el1 =3D deposit64(env->cp15.mdscr_el1, 2, 4, moe); } =20 + if (env->exception.target_el =3D=3D 2) { + arm_cpu_do_interrupt_aarch32_hyp(cs); + return; + } + /* TODO: Vectored interrupt controller. */ switch (cs->exception_index) { case EXCP_UDEF: --=20 2.18.0