From nobody Tue Apr 15 15:44:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535103959126760.9711278772272; Fri, 24 Aug 2018 02:45:59 -0700 (PDT) Received: from localhost ([::1]:40719 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ft8f8-0000Au-Vg for importer@patchew.org; Fri, 24 Aug 2018 05:45:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35443) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ft8Tm-0007Cd-RZ for qemu-devel@nongnu.org; Fri, 24 Aug 2018 05:34:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ft8Tl-0003bt-Lz for qemu-devel@nongnu.org; Fri, 24 Aug 2018 05:34:06 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44874) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ft8Tl-0003ZB-CV for qemu-devel@nongnu.org; Fri, 24 Aug 2018 05:34:05 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ft8Tk-0006S4-E0 for qemu-devel@nongnu.org; Fri, 24 Aug 2018 10:34:04 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 24 Aug 2018 10:33:06 +0100 Message-Id: <20180824093343.11346-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180824093343.11346-1-peter.maydell@linaro.org> References: <20180824093343.11346-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 15/52] target/arm: Factor out code for taking an AArch32 exception X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Factor out the code which changes the CPU state so as to actually take an exception to AArch32. We're going to want to use this for handling exception entry to Hyp mode. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Reviewed-by: Luc Michel Message-id: 20180820153020.21478-4-peter.maydell@linaro.org --- target/arm/helper.c | 64 +++++++++++++++++++++++++++++---------------- 1 file changed, 41 insertions(+), 23 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0d5f6f48cfe..b47657c31b2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8033,6 +8033,46 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->regs[15] =3D env->pc; } =20 +static void take_aarch32_exception(CPUARMState *env, int new_mode, + uint32_t mask, uint32_t offset, + uint32_t newpc) +{ + /* Change the CPU state so as to actually take the exception. */ + switch_mode(env, new_mode); + /* + * For exceptions taken to AArch32 we must clear the SS bit in both + * PSTATE and in the old-state value we save to SPSR_, so zero i= t now. + */ + env->uncached_cpsr &=3D ~PSTATE_SS; + env->spsr =3D cpsr_read(env); + /* Clear IT bits. */ + env->condexec_bits =3D 0; + /* Switch to the new mode, and to the correct instruction set. */ + env->uncached_cpsr =3D (env->uncached_cpsr & ~CPSR_M) | new_mode; + /* Set new mode endianness */ + env->uncached_cpsr &=3D ~CPSR_E; + if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { + env->uncached_cpsr |=3D CPSR_E; + } + env->daif |=3D mask; + + if (new_mode =3D=3D ARM_CPU_MODE_HYP) { + env->thumb =3D (env->cp15.sctlr_el[2] & SCTLR_TE) !=3D 0; + env->elr_el[2] =3D env->regs[15]; + } else { + /* + * this is a lie, as there was no c1_sys on V4T/V5, but who cares + * and we should just guard the thumb mode on V4 + */ + if (arm_feature(env, ARM_FEATURE_V4T)) { + env->thumb =3D + (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) !=3D 0; + } + env->regs[14] =3D env->regs[15] + offset; + } + env->regs[15] =3D newpc; +} + static void arm_cpu_do_interrupt_aarch32(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -8175,29 +8215,7 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *c= s) env->cp15.scr_el3 &=3D ~SCR_NS; } =20 - switch_mode (env, new_mode); - /* For exceptions taken to AArch32 we must clear the SS bit in both - * PSTATE and in the old-state value we save to SPSR_, so zero i= t now. - */ - env->uncached_cpsr &=3D ~PSTATE_SS; - env->spsr =3D cpsr_read(env); - /* Clear IT bits. */ - env->condexec_bits =3D 0; - /* Switch to the new mode, and to the correct instruction set. */ - env->uncached_cpsr =3D (env->uncached_cpsr & ~CPSR_M) | new_mode; - /* Set new mode endianness */ - env->uncached_cpsr &=3D ~CPSR_E; - if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { - env->uncached_cpsr |=3D CPSR_E; - } - env->daif |=3D mask; - /* this is a lie, as the was no c1_sys on V4T/V5, but who cares - * and we should just guard the thumb mode on V4 */ - if (arm_feature(env, ARM_FEATURE_V4T)) { - env->thumb =3D (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE)= !=3D 0; - } - env->regs[14] =3D env->regs[15] + offset; - env->regs[15] =3D addr; + take_aarch32_exception(env, new_mode, mask, offset, addr); } =20 /* Handle exception entry to a target EL which is using AArch64 */ --=20 2.18.0