From nobody Wed Nov 5 13:02:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1535034402516976.5891785343001; Thu, 23 Aug 2018 07:26:42 -0700 (PDT) Received: from localhost ([::1]:36827 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fsqZJ-0004O7-U5 for importer@patchew.org; Thu, 23 Aug 2018 10:26:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50782) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fsq0k-0003EZ-Us for qemu-devel@nongnu.org; Thu, 23 Aug 2018 09:50:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fsq0k-0003VM-5p for qemu-devel@nongnu.org; Thu, 23 Aug 2018 09:50:54 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44844) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fsq0i-0003TW-6r; Thu, 23 Aug 2018 09:50:52 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fsq0f-0005r3-Ps; Thu, 23 Aug 2018 14:50:49 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 23 Aug 2018 14:50:47 +0100 Message-Id: <20180823135047.16525-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH] target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ARMv8 architecture defines that an AArch32 CPU starts in SVC mode, unless EL2 is the highest available EL, in which case it starts in Hyp mode. (In ARMv7 a CPU with EL2 but not EL3 was not a valid configuration, but we don't specifically reject this if the user asks for one.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 258ba6dcaad..b5e61cc1775 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -199,8 +199,18 @@ static void arm_cpu_reset(CPUState *s) env->cp15.c15_cpar =3D 1; } #else - /* SVC mode with interrupts disabled. */ - env->uncached_cpsr =3D ARM_CPU_MODE_SVC; + + /* + * If the highest available EL is EL2, AArch32 will start in Hyp + * mode; otherwise it starts in SVC. Note that if we start in + * AArch64 then these values in the uncached_cpsr will be ignored. + */ + if (arm_feature(env, ARM_FEATURE_EL2) && + !arm_feature(env, ARM_FEATURE_EL3)) { + env->uncached_cpsr =3D ARM_CPU_MODE_HYP; + } else { + env->uncached_cpsr =3D ARM_CPU_MODE_SVC; + } env->daif =3D PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; =20 if (arm_feature(env, ARM_FEATURE_M)) { --=20 2.18.0