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[64.112.177.9]) by smtp.gmail.com with ESMTPSA id 62-v6sm1217660qkx.66.2018.08.22.07.40.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 22 Aug 2018 07:40:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DHL3Zcwss0piFlDFYYhvTKui+H42kSvp+qfuGFaFUFo=; b=GuO3DVmpTodR5MQPVfoHdkeUY1ojlvOIJnx3W/63Zhrl1anssReddBrxouJTTolou/ XX1Vk+0LJ3EowaMV/xLxTQj7y9vjyvJ3DF5dn/wOPy9/46804OZtgiS8P5XnGI9P0Rds SP6Y3U8hmDURQSzhMP0g02gqK737gNAy6yhAHV6IeWNgGr8ri9/AESBHHcAKwpPvr6jD a6uuKiNcrThxk0myZK5rY+TmmHLYH+UmufE9lAu0ipressOE6UwwTiQtapfXb198mAnG RmmwtAEUC7xIZU8QhafxipHk6/dm+8ChK7R7L5ViLOTzblNdeVcR69DWFN6g6/TnOodA 0yhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DHL3Zcwss0piFlDFYYhvTKui+H42kSvp+qfuGFaFUFo=; b=VgOI3ZoxVzViUplwdlbw0TdhHgi+kftnffgsAx8xjwNP2wxP3xu1My/SRuQPX/Fh+s V/rXcz55+9HzXrgZNJ51G8051YCGsMbycuC9SjlPN8+brJq+6dnYq5ytF+1hOSEMXhZt QhhOnpfjiSnSCyRdV1il3keBNsMISRNpQhG1NsjzA84ValVyXIBt85i1RXxHWw2iVQNk OWUjmS15+/Hbadmqt9I/83F/5InntincEG7Wv0151oumzJq+ZPmdkWi8EfF2oFLHAALl clcP9k2DROET55xW69FcXfSDaAVwoeThfd7gTD4Phb4ks/T4G9VHienEA4wmmQcZh//n Jvwg== X-Gm-Message-State: AOUpUlGzNeRMU6G6naOP47AAhLnUxytQO+DfrNdoPwH/Ar03sQNuiUU0 J73H4lNminxTxrhHzDnbBJbrNlk1foY= X-Google-Smtp-Source: AA+uWPyf99tMiMVuW0SZV0dJATBQcHu9TWp341GKTSlhDJm4KgOLyDqh5HrrE4fLpe/LchWAAD2cuA== X-Received: by 2002:a0c:b65a:: with SMTP id q26-v6mr51653409qvf.43.1534948859220; Wed, 22 Aug 2018 07:40:59 -0700 (PDT) From: Pavel Zbitskiy To: qemu-devel@nongnu.org Date: Wed, 22 Aug 2018 10:40:38 -0400 Message-Id: <20180822144039.5796-3-pavel.zbitskiy@gmail.com> In-Reply-To: <20180822144039.5796-1-pavel.zbitskiy@gmail.com> References: <20180822144039.5796-1-pavel.zbitskiy@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::242 Subject: [Qemu-devel] [PATCH v4 2/3] target/s390x: exception on non-aligned LPSW(E) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Pavel Zbitskiy , david@redhat.com, cohuck@redhat.com, richard.henderson@linaro.org, Alexander Graf , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Both LPSW and LPSWE should raise a specification exception when their operand is not doubleword aligned. This could've been done without a helper, but this would introduce a new basic block, which would require making o->in2 local. This could've also been done in load_psw helper, but this is too late - specification exception should be recognized before memory accesses take place. Signed-off-by: Pavel Zbitskiy --- target/s390x/helper.h | 1 + target/s390x/mem_helper.c | 19 ++++++++++++------- target/s390x/translate.c | 8 ++++++++ 3 files changed, 21 insertions(+), 7 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 97c60ca7bc..b0df3267e5 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -120,6 +120,7 @@ DEF_HELPER_4(cu41, i32, env, i32, i32, i32) DEF_HELPER_4(cu42, i32, env, i32, i32, i32) DEF_HELPER_5(msa, i32, env, i32, i32, i32, i32) DEF_HELPER_FLAGS_1(stpt, TCG_CALL_NO_RWG, i64, env) +DEF_HELPER_FLAGS_3(check_alignment, TCG_CALL_NO_RWG, void, env, i64, i32) =20 #ifndef CONFIG_USER_ONLY DEF_HELPER_3(servc, i32, env, i64, i64) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index bacae4f503..75ca1997ad 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -81,13 +81,18 @@ static inline uint32_t adj_len_to_page(uint32_t len, ui= nt64_t addr) /* Trigger a SPECIFICATION exception if an address or a length is not naturally aligned. */ static inline void check_alignment(CPUS390XState *env, uint64_t v, - int wordsize, uintptr_t ra) + uint32_t wordsize, int ilen, uintptr_t = ra) { if (v % wordsize) { - s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); + s390_program_interrupt(env, PGM_SPECIFICATION, ilen, ra); } } =20 +void HELPER(check_alignment)(CPUS390XState *env, uint64_t v, uint32_t word= size) +{ + check_alignment(env, v, wordsize, ILEN_AUTO, GETPC()); +} + /* Load a value from memory according to its size. */ static inline uint64_t cpu_ldusize_data_ra(CPUS390XState *env, uint64_t ad= dr, int wordsize, uintptr_t ra) @@ -847,7 +852,7 @@ static inline uint32_t do_clcl(CPUS390XState *env, uint64_t len =3D MAX(*src1len, *src3len); uint32_t cc =3D 0; =20 - check_alignment(env, *src1len | *src3len, wordsize, ra); + check_alignment(env, *src1len | *src3len, wordsize, 6, ra); =20 if (!len) { return cc; @@ -1348,7 +1353,7 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r1= , uint32_t r2, tbl &=3D -8; } =20 - check_alignment(env, len, ssize, ra); + check_alignment(env, len, ssize, 6, ra); =20 /* Lest we fail to service interrupts in a timely manner, */ /* limit the amount of work we're willing to do. */ @@ -1400,7 +1405,7 @@ static void do_cdsg(CPUS390XState *env, uint64_t addr, } else { uint64_t oldh, oldl; =20 - check_alignment(env, addr, 16, ra); + check_alignment(env, addr, 16, 6, ra); =20 oldh =3D cpu_ldq_data_ra(env, addr + 0, ra); oldl =3D cpu_ldq_data_ra(env, addr + 8, ra); @@ -2116,7 +2121,7 @@ static uint64_t do_lpq(CPUS390XState *env, uint64_t a= ddr, bool parallel) lo =3D int128_getlo(v); #endif } else { - check_alignment(env, addr, 16, ra); + check_alignment(env, addr, 16, 6, ra); =20 hi =3D cpu_ldq_data_ra(env, addr + 0, ra); lo =3D cpu_ldq_data_ra(env, addr + 8, ra); @@ -2153,7 +2158,7 @@ static void do_stpq(CPUS390XState *env, uint64_t addr, helper_atomic_sto_be_mmu(env, addr, v, oi, ra); #endif } else { - check_alignment(env, addr, 16, ra); + check_alignment(env, addr, 16, 6, ra); =20 cpu_stq_data_ra(env, addr + 0, high, ra); cpu_stq_data_ra(env, addr + 8, low, ra); diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 7363aabf3a..4161bd0b1f 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -2828,9 +2828,13 @@ static DisasJumpType op_lpp(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_lpsw(DisasContext *s, DisasOps *o) { + TCGv_i32 t0; TCGv_i64 t1, t2; =20 check_privileged(s); + t0 =3D tcg_const_i32(8); + gen_helper_check_alignment(cpu_env, o->in2, t0); + tcg_temp_free_i32(t0); per_breaking_event(s); =20 t1 =3D tcg_temp_new_i64(); @@ -2848,9 +2852,13 @@ static DisasJumpType op_lpsw(DisasContext *s, DisasO= ps *o) =20 static DisasJumpType op_lpswe(DisasContext *s, DisasOps *o) { + TCGv_i32 t0; TCGv_i64 t1, t2; =20 check_privileged(s); + t0 =3D tcg_const_i32(8); + gen_helper_check_alignment(cpu_env, o->in2, t0); + tcg_temp_free_i32(t0); per_breaking_event(s); =20 t1 =3D tcg_temp_new_i64(); --=20 2.18.0