From nobody Wed Nov 5 13:00:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534860097955223.90259762419498; Tue, 21 Aug 2018 07:01:37 -0700 (PDT) Received: from localhost ([::1]:53769 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs7Dv-0003aL-L4 for importer@patchew.org; Tue, 21 Aug 2018 10:01:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60576) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs6i8-00064x-Hi for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:28:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fs6i7-0003vv-Nw for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:28:40 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44756) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fs6i3-0003S5-Nb; Tue, 21 Aug 2018 09:28:35 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fs6hj-000492-F9; Tue, 21 Aug 2018 14:28:15 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 14:28:03 +0100 Message-Id: <20180821132811.17675-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180821132811.17675-1-peter.maydell@linaro.org> References: <20180821132811.17675-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 1/9] hw/intc/arm_gic: Document QEMU interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The GICv2's QEMU interface (sysbus MMIO regions, IRQs, etc) is now quite complicated with the addition of the virtualization extensions. Add a comment in the header file which documents it. Signed-off-by: Peter Maydell --- I needed to write this out to figure out what I was connecting to what in the a15mpcore object :-) --- include/hw/intc/arm_gic.h | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h index 42bb535fd45..989bc837606 100644 --- a/include/hw/intc/arm_gic.h +++ b/include/hw/intc/arm_gic.h @@ -18,6 +18,41 @@ * with this program; if not, see . */ =20 +/* + * QEMU interface: + * + QOM property "num-cpu": number of CPUs to support + * + QOM property "num-irq": number of IRQs (including both SPIs and PPIs) + * + QOM property "revision": GIC version (1 or 2), or 0 for the 11MPCore= GIC + * + QOM property "has-security-extensions": set true if the GIC should + * implement the security extensions + * + QOM property "has-virtualization-extensions": set true if the GIC sh= ould + * implement the virtualization extensions + * + unnamed GPIO inputs: (where P is number of PPIs, i.e. num-irq - 32) + * [0..P-1] SPIs + * [P..P+31] PPIs for CPU 0 + * [P+32..P+63] PPIs for CPU 1 + * ... + * + sysbus IRQ 0 : IRQ + * + sysbus IRQ 1 : FIQ + * + sysbus IRQ 2 : VIRQ (exists even if virt extensions not present) + * + sysbus IRQ 3 : VFIQ (exists even if virt extensions not present) + * + sysbus IRQ 4 : maintenance IRQ for CPU i/f 0 (only if virt extns pre= sent) + * + sysbus IRQ 5 : maintenance IRQ for CPU i/f 1 (only if virt extns pre= sent) + * ... + * + sysbus MMIO regions: (in order; numbers will vary depending on + * whether virtualization extensions are present and on number of cores) + * - distributor registers (GICD*) + * - CPU interface for the accessing core (GICC*) + * - virtual interface control registers (GICH*) (only if virt extns pr= esent) + * - virtual CPU interface for the accessing core (GICV*) (only if virt) + * - CPU 0 CPU interface registers + * - CPU 1 CPU interface registers + * ... + * - CPU 0 VCPU interface registers (only if virt extns present) + * - CPU 1 VCPU interface registers (only if virt extns present) + * ... + */ + #ifndef HW_ARM_GIC_H #define HW_ARM_GIC_H =20 --=20 2.18.0 From nobody Wed Nov 5 13:00:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534860592369181.47466563558623; Tue, 21 Aug 2018 07:09:52 -0700 (PDT) Received: from localhost ([::1]:53812 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs7Lz-0004e3-2E for importer@patchew.org; Tue, 21 Aug 2018 10:09:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60547) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs6i6-000639-JQ for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:28:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fs6i4-0003sQ-D2 for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:28:38 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44756) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fs6i2-0003S5-Pj; Tue, 21 Aug 2018 09:28:34 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fs6hk-00049L-Ct; Tue, 21 Aug 2018 14:28:16 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 14:28:04 +0100 Message-Id: <20180821132811.17675-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180821132811.17675-1-peter.maydell@linaro.org> References: <20180821132811.17675-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 2/9] hw/intc/arm_gic: Make per-cpu GICH memory regions 0x200 bytes large X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reduce the size of the per-cpu GICH memory regions from 0x1000 to 0x200. The registers only cover 0x200 bytes, and the Cortex-A15 wants to map them at a spacing of 0x200 bytes apart. Having the region be too large interferes with mapping them like that, so reduce it. Signed-off-by: Peter Maydell Reviewed-By: Luc Michel --- hw/intc/arm_gic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index c1b35fc1ee2..542b4b93eab 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -2084,7 +2084,7 @@ static void arm_gic_realize(DeviceState *dev, Error *= *errp) for (i =3D 0; i < s->num_cpu; i++) { memory_region_init_io(&s->vifaceiomem[i + 1], OBJECT(s), &gic_viface_ops, &s->backref[i], - "gic_viface", 0x1000); + "gic_viface", 0x200); sysbus_init_mmio(sbd, &s->vifaceiomem[i + 1]); } } --=20 2.18.0 From nobody Wed Nov 5 13:00:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534860420130144.1914241283739; Tue, 21 Aug 2018 07:07:00 -0700 (PDT) Received: from localhost ([::1]:53800 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs7J9-00023h-1S for importer@patchew.org; Tue, 21 Aug 2018 10:06:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60526) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs6i4-00060L-97 for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:28:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fs6i3-0003rf-Ji for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:28:36 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44756) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fs6i1-0003S5-OX; Tue, 21 Aug 2018 09:28:33 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fs6hl-0004A8-Am; Tue, 21 Aug 2018 14:28:17 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 14:28:05 +0100 Message-Id: <20180821132811.17675-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180821132811.17675-1-peter.maydell@linaro.org> References: <20180821132811.17675-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 3/9] hw/arm/vexpress: Connect VIRQ and VFIQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Connect the VIRQ and VFIQ lines from the GIC to the CPU; these exist always for both CPU and GIC whether the virtualization extensions are enabled or not, so we can just unconditionally connect them. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel --- hw/arm/vexpress.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 5bfe2e43487..dc47ed84c20 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -251,6 +251,10 @@ static void init_cpus(const char *cpu_type, const char= *privdev, sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ= )); sysbus_connect_irq(busdev, n + smp_cpus, qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); + sysbus_connect_irq(busdev, n + 2 * smp_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); + sysbus_connect_irq(busdev, n + 3 * smp_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); } } =20 --=20 2.18.0 From nobody Wed Nov 5 13:00:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153485988764841.46869458302092; Tue, 21 Aug 2018 06:58:07 -0700 (PDT) Received: from localhost ([::1]:53745 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs7Ac-00075E-EU for importer@patchew.org; Tue, 21 Aug 2018 09:58:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60531) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs6i4-00060c-FL for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:28:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fs6i2-0003qE-RV for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:28:36 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44756) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fs6i0-0003S5-KQ; Tue, 21 Aug 2018 09:28:32 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fs6hm-0004Ad-AW; Tue, 21 Aug 2018 14:28:18 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 14:28:06 +0100 Message-Id: <20180821132811.17675-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180821132811.17675-1-peter.maydell@linaro.org> References: <20180821132811.17675-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 4/9] hw/arm/highbank: Connect VIRQ and VFIQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Connect the VIRQ and VFIQ lines from the GIC to the CPU; these exist always for both CPU and GIC whether the virtualization extensions are enabled or not, so we can just unconditionally connect them. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel --- hw/arm/highbank.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 6d42fce2c37..fb9efa02c35 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -243,6 +243,8 @@ static void calxeda_init(MachineState *machine, enum cx= machines machine_id) int n; qemu_irq cpu_irq[4]; qemu_irq cpu_fiq[4]; + qemu_irq cpu_virq[4]; + qemu_irq cpu_vfiq[4]; MemoryRegion *sysram; MemoryRegion *dram; MemoryRegion *sysmem; @@ -282,6 +284,8 @@ static void calxeda_init(MachineState *machine, enum cx= machines machine_id) object_property_set_bool(cpuobj, true, "realized", &error_fatal); cpu_irq[n] =3D qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ); cpu_fiq[n] =3D qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ); + cpu_virq[n] =3D qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VIRQ); + cpu_vfiq[n] =3D qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VFIQ); } =20 sysmem =3D get_system_memory(); @@ -329,6 +333,8 @@ static void calxeda_init(MachineState *machine, enum cx= machines machine_id) for (n =3D 0; n < smp_cpus; n++) { sysbus_connect_irq(busdev, n, cpu_irq[n]); sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]); + sysbus_connect_irq(busdev, n + 2 * smp_cpus, cpu_virq[n]); + sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]); } =20 for (n =3D 0; n < 128; n++) { --=20 2.18.0 From nobody Wed Nov 5 13:00:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534860229074346.72525937924127; Tue, 21 Aug 2018 07:03:49 -0700 (PDT) Received: from localhost ([::1]:53782 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs7G7-0006qu-V3 for importer@patchew.org; Tue, 21 Aug 2018 10:03:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60485) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs6i2-0005y8-GC for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:28:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fs6i1-0003oE-Rr for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:28:34 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44756) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fs6hz-0003S5-Ex; Tue, 21 Aug 2018 09:28:31 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fs6hn-0004B6-9j; Tue, 21 Aug 2018 14:28:19 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 14:28:07 +0100 Message-Id: <20180821132811.17675-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180821132811.17675-1-peter.maydell@linaro.org> References: <20180821132811.17675-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 5/9] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Connect the VIRQ and VFIQ lines from the GIC to the CPU; these exist always for both CPU and GIC whether the virtualization extensions are enabled or not, so we can just unconditionally connect them. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel --- hw/arm/fsl-imx6ul.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index 258f4706234..4b56bfa8d16 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -207,6 +207,10 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error= **errp) irq =3D qdev_get_gpio_in(d, ARM_CPU_IRQ); sysbus_connect_irq(sbd, i, irq); sysbus_connect_irq(sbd, i + smp_cpus, qdev_get_gpio_in(d, ARM_CPU_= FIQ)); + sysbus_connect_irq(sbd, i + 2 * smp_cpus, + qdev_get_gpio_in(d, ARM_CPU_VIRQ)); + sysbus_connect_irq(sbd, i + 3 * smp_cpus, + qdev_get_gpio_in(d, ARM_CPU_VFIQ)); } =20 /* --=20 2.18.0 From nobody Wed Nov 5 13:00:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534859694179707.6630033870687; Tue, 21 Aug 2018 06:54:54 -0700 (PDT) Received: from localhost ([::1]:53724 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs77R-00046O-0A for importer@patchew.org; Tue, 21 Aug 2018 09:54:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60460) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs6i1-0005xZ-UK for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:28:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fs6i0-0003mY-MZ for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:28:33 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44756) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fs6hx-0003S5-GJ; Tue, 21 Aug 2018 09:28:29 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fs6ho-0004Ba-71; Tue, 21 Aug 2018 14:28:20 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 14:28:08 +0100 Message-Id: <20180821132811.17675-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180821132811.17675-1-peter.maydell@linaro.org> References: <20180821132811.17675-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 6/9] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Connect the VIRQ and VFIQ lines from the GIC to the CPU; these exist always for both CPU and GIC whether the virtualization extensions are enabled or not, so we can just unconditionally connect them. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel --- hw/arm/fsl-imx7.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index d5e26855a55..7663ad68610 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -209,6 +209,10 @@ static void fsl_imx7_realize(DeviceState *dev, Error *= *errp) sysbus_connect_irq(sbd, i, irq); irq =3D qdev_get_gpio_in(d, ARM_CPU_FIQ); sysbus_connect_irq(sbd, i + smp_cpus, irq); + irq =3D qdev_get_gpio_in(d, ARM_CPU_VIRQ); + sysbus_connect_irq(sbd, i + 2 * smp_cpus, irq); + irq =3D qdev_get_gpio_in(d, ARM_CPU_VFIQ); + sysbus_connect_irq(sbd, i + 3 * smp_cpus, irq); } =20 /* --=20 2.18.0 From nobody Wed Nov 5 13:00:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534859163145601.1132291954884; Tue, 21 Aug 2018 06:46:03 -0700 (PDT) Received: from localhost ([::1]:53674 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs6yw-0005h1-0h for importer@patchew.org; Tue, 21 Aug 2018 09:46:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60436) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs6i0-0005wE-NM for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:28:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fs6hz-0003jx-Hr for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:28:32 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44756) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fs6hw-0003S5-3W; Tue, 21 Aug 2018 09:28:28 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fs6hp-0004C3-46; Tue, 21 Aug 2018 14:28:21 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 14:28:09 +0100 Message-Id: <20180821132811.17675-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180821132811.17675-1-peter.maydell@linaro.org> References: <20180821132811.17675-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 7/9] hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For the A15MPCore internal peripheral object, we handle GIC security extensions support by checking whether the CPUs have EL3 enabled; if so then we enable it also on the GIC. Handle the virtualization extensions in the same way: if the CPU has EL2 then enable it on the GIC and wire up the virtualization-specific memory regions and the maintenance interrupt. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel --- hw/cpu/a15mpcore.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index 43c10794938..226ce8900f2 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -53,6 +53,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **= errp) int i; Error *err =3D NULL; bool has_el3; + bool has_el2; Object *cpuobj; =20 gicdev =3D DEVICE(&s->gic); @@ -67,6 +68,10 @@ static void a15mp_priv_realize(DeviceState *dev, Error *= *errp) has_el3 =3D object_property_find(cpuobj, "has_el3", NULL) && object_property_get_bool(cpuobj, "has_el3", &error_abort); qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); + /* Similarly for virtualization support */ + has_el2 =3D object_property_find(cpuobj, "has_el2", NULL) && + object_property_get_bool(cpuobj, "has_el2", &error_abort); + qdev_prop_set_bit(gicdev, "has-virtualization-extensions", has_el2= ); } =20 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); @@ -103,20 +108,40 @@ static void a15mp_priv_realize(DeviceState *dev, Erro= r **errp) qdev_get_gpio_in(gicdev, ppibase + timer_irq[irq= ])); } + if (has_el2) { + /* Connect the GIC maintenance interrupt to PPI ID 25 */ + sysbus_connect_irq(SYS_BUS_DEVICE(gicdev), i + 4 * s->num_cpu, + qdev_get_gpio_in(gicdev, ppibase + 25)); + } } =20 /* Memory map (addresses are offsets from PERIPHBASE): * 0x0000-0x0fff -- reserved * 0x1000-0x1fff -- GIC Distributor * 0x2000-0x3fff -- GIC CPU interface - * 0x4000-0x4fff -- GIC virtual interface control (not modelled) - * 0x5000-0x5fff -- GIC virtual interface control (not modelled) - * 0x6000-0x7fff -- GIC virtual CPU interface (not modelled) + * 0x4000-0x4fff -- GIC virtual interface control for this CPU + * 0x5000-0x51ff -- GIC virtual interface control for CPU 0 + * 0x5200-0x53ff -- GIC virtual interface control for CPU 1 + * 0x5400-0x55ff -- GIC virtual interface control for CPU 2 + * 0x5600-0x57ff -- GIC virtual interface control for CPU 3 + * 0x6000-0x7fff -- GIC virtual CPU interface */ memory_region_add_subregion(&s->container, 0x1000, sysbus_mmio_get_region(busdev, 0)); memory_region_add_subregion(&s->container, 0x2000, sysbus_mmio_get_region(busdev, 1)); + if (has_el2) { + memory_region_add_subregion(&s->container, 0x4000, + sysbus_mmio_get_region(busdev, 2)); + memory_region_add_subregion(&s->container, 0x6000, + sysbus_mmio_get_region(busdev, 3)); + for (i =3D 0; i < s->num_cpu; i++) { + hwaddr base =3D 0x5000 + i * 0x200; + MemoryRegion *mr =3D sysbus_mmio_get_region(busdev, + 4 + s->num_cpu + i); + memory_region_add_subregion(&s->container, base, mr); + } + } } =20 static Property a15mp_priv_properties[] =3D { --=20 2.18.0 From nobody Wed Nov 5 13:00:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534858990986456.7019876586219; Tue, 21 Aug 2018 06:43:10 -0700 (PDT) Received: from localhost ([::1]:53655 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs6w9-0003KA-Mm for importer@patchew.org; Tue, 21 Aug 2018 09:43:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60402) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs6hz-0005uo-J0 for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:28:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fs6hy-0003ij-0r for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:28:31 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44756) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fs6hu-0003S5-On; Tue, 21 Aug 2018 09:28:26 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fs6hq-0004CW-1V; Tue, 21 Aug 2018 14:28:22 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 14:28:10 +0100 Message-Id: <20180821132811.17675-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180821132811.17675-1-peter.maydell@linaro.org> References: <20180821132811.17675-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 8/9] hw/arm/vexpress: Don't set info->secure_boot if CPU doesn't have EL3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Don't request that the arm_load_kernel() code should boot in secure state if the CPU doesn't have a secure state. Currently this doesn't make a difference because the boot.c code only examines the secure_boot flag in code guarded by an ARM_FEATURE_EL3 check, but upcoming changes for supporting booting into Hyp mode will change that. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel --- hw/arm/vexpress.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index dc47ed84c20..3631f4de3a4 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -705,8 +705,8 @@ static void vexpress_common_init(MachineState *machine) daughterboard->bootinfo.smp_bootreg_addr =3D map[VE_SYSREGS] + 0x30; daughterboard->bootinfo.gic_cpu_if_addr =3D daughterboard->gic_cpu_if_= addr; daughterboard->bootinfo.modify_dtb =3D vexpress_modify_dtb; - /* Indicate that when booting Linux we should be in secure state */ - daughterboard->bootinfo.secure_boot =3D true; + /* When booting Linux we should be in secure state if the CPU has one.= */ + daughterboard->bootinfo.secure_boot =3D vms->secure; arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo); } =20 --=20 2.18.0 From nobody Wed Nov 5 13:00:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534859463602976.0586986177381; Tue, 21 Aug 2018 06:51:03 -0700 (PDT) Received: from localhost ([::1]:53706 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs73m-0000sY-GB for importer@patchew.org; Tue, 21 Aug 2018 09:51:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60375) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fs6hx-0005sO-Eb for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:28:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fs6hw-0003fe-4t for qemu-devel@nongnu.org; Tue, 21 Aug 2018 09:28:29 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44756) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fs6ht-0003S5-OT; Tue, 21 Aug 2018 09:28:25 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fs6hr-0004Cm-1S; Tue, 21 Aug 2018 14:28:23 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 14:28:11 +0100 Message-Id: <20180821132811.17675-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180821132811.17675-1-peter.maydell@linaro.org> References: <20180821132811.17675-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 9/9] hw/arm/vexpress: Add "virtualization" property controlling presence of EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add a "virtualization" property to the vexpress-a15 board, controlling presence of EL2. As with EL3, we default to enabling it, but the user can disable it if they have an older guest which can't cope with it being present. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel --- hw/arm/vexpress.c | 56 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 53 insertions(+), 3 deletions(-) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 3631f4de3a4..c02d18ee618 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -172,6 +172,7 @@ typedef struct { typedef struct { MachineState parent; bool secure; + bool virt; } VexpressMachineState; =20 #define TYPE_VEXPRESS_MACHINE "vexpress" @@ -203,7 +204,7 @@ struct VEDBoardInfo { }; =20 static void init_cpus(const char *cpu_type, const char *privdev, - hwaddr periphbase, qemu_irq *pic, bool secure) + hwaddr periphbase, qemu_irq *pic, bool secure, bool = virt) { DeviceState *dev; SysBusDevice *busdev; @@ -216,6 +217,11 @@ static void init_cpus(const char *cpu_type, const char= *privdev, if (!secure) { object_property_set_bool(cpuobj, false, "has_el3", NULL); } + if (!virt) { + if (object_property_find(cpuobj, "has_el2", NULL)) { + object_property_set_bool(cpuobj, false, "has_el2", NULL); + } + } =20 if (object_property_find(cpuobj, "reset-cbar", NULL)) { object_property_set_int(cpuobj, periphbase, @@ -289,7 +295,8 @@ static void a9_daughterboard_init(const VexpressMachine= State *vms, memory_region_add_subregion(sysmem, 0x60000000, ram); =20 /* 0x1e000000 A9MPCore (SCU) private memory region */ - init_cpus(cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure); + init_cpus(cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, + vms->secure, vms->virt); =20 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ =20 @@ -370,7 +377,8 @@ static void a15_daughterboard_init(const VexpressMachin= eState *vms, memory_region_add_subregion(sysmem, 0x80000000, ram); =20 /* 0x2c000000 A15MPCore private memory region (GIC) */ - init_cpus(cpu_type, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure); + init_cpus(cpu_type, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure, + vms->virt); =20 /* A15 daughterboard peripherals: */ =20 @@ -724,6 +732,20 @@ static void vexpress_set_secure(Object *obj, bool valu= e, Error **errp) vms->secure =3D value; } =20 +static bool vexpress_get_virt(Object *obj, Error **errp) +{ + VexpressMachineState *vms =3D VEXPRESS_MACHINE(obj); + + return vms->virt; +} + +static void vexpress_set_virt(Object *obj, bool value, Error **errp) +{ + VexpressMachineState *vms =3D VEXPRESS_MACHINE(obj); + + vms->virt =3D value; +} + static void vexpress_instance_init(Object *obj) { VexpressMachineState *vms =3D VEXPRESS_MACHINE(obj); @@ -738,6 +760,32 @@ static void vexpress_instance_init(Object *obj) NULL); } =20 +static void vexpress_a15_instance_init(Object *obj) +{ + VexpressMachineState *vms =3D VEXPRESS_MACHINE(obj); + + /* + * For the vexpress-a15, EL2 is by default enabled if EL3 is, + * but can also be specifically set to on or off. + */ + vms->virt =3D true; + object_property_add_bool(obj, "virtualization", vexpress_get_virt, + vexpress_set_virt, NULL); + object_property_set_description(obj, "virtualization", + "Set on/off to enable/disable the ARM " + "Virtualization Extensions " + "(defaults to same as 'secure')", + NULL); +} + +static void vexpress_a9_instance_init(Object *obj) +{ + VexpressMachineState *vms =3D VEXPRESS_MACHINE(obj); + + /* The A9 doesn't have the virt extensions */ + vms->virt =3D false; +} + static void vexpress_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -784,12 +832,14 @@ static const TypeInfo vexpress_a9_info =3D { .name =3D TYPE_VEXPRESS_A9_MACHINE, .parent =3D TYPE_VEXPRESS_MACHINE, .class_init =3D vexpress_a9_class_init, + .instance_init =3D vexpress_a9_instance_init, }; =20 static const TypeInfo vexpress_a15_info =3D { .name =3D TYPE_VEXPRESS_A15_MACHINE, .parent =3D TYPE_VEXPRESS_MACHINE, .class_init =3D vexpress_a15_class_init, + .instance_init =3D vexpress_a15_instance_init, }; =20 static void vexpress_machine_init(void) --=20 2.18.0