From nobody Wed Apr 16 16:03:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534761297068815.4439116160352; Mon, 20 Aug 2018 03:34:57 -0700 (PDT) Received: from localhost ([::1]:46027 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1frhWE-00054T-4L for importer@patchew.org; Mon, 20 Aug 2018 06:34:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36992) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1frhU4-0003kv-OU for qemu-devel@nongnu.org; Mon, 20 Aug 2018 06:32:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1frhU3-0005UV-Mo for qemu-devel@nongnu.org; Mon, 20 Aug 2018 06:32:28 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44566) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1frhU3-0005PL-2C for qemu-devel@nongnu.org; Mon, 20 Aug 2018 06:32:27 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1frhTz-00037Q-KY for qemu-devel@nongnu.org; Mon, 20 Aug 2018 11:32:23 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 20 Aug 2018 11:31:54 +0100 Message-Id: <20180820103212.2810-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180820103212.2810-1-peter.maydell@linaro.org> References: <20180820103212.2810-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 07/25] target/arm: Implement AArch32 HVBAR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement the AArch32 HVBAR register; we can do this just by making the existing VBAR_EL2 regdefs be STATE_BOTH. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Luc Michel Message-id: 20180814124254.5229-5-peter.maydell@linaro.org --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a68577a06aa..274fb219122 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3750,7 +3750,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { =20 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] =3D { - { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_AA64, + { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, .access =3D PL2_RW, .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }, @@ -3899,7 +3899,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, - { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_AA64, + { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, .access =3D PL2_RW, .writefn =3D vbar_write, .fieldoffset =3D offsetof(CPUARMState, cp15.vbar_el[2]), --=20 2.18.0