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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Mon, 20 Aug 2018 11:32:01 +0100
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Subject: [Qemu-devel] [PULL 14/25] hw/ssi/xilinx_spips: Remove unneeded MMIO
request_ptr code
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We now support direct execution from MMIO regions in the
core memory subsystem. This means that we don't need to
have device-specific support for it, and we can remove
the request_ptr handling from the Xilinx SPIPS device.
(It was broken anyway due to race conditions, and disabled
by default.)
This device is the only in-tree user of this API.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>
Message-id: 20180817114619.22354-2-peter.maydell@linaro.org
---
hw/ssi/xilinx_spips.c | 46 -------------------------------------------
1 file changed, 46 deletions(-)
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index c052bfc4b3c..16f88f74029 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -1031,14 +1031,6 @@ static const MemoryRegionOps spips_ops =3D {
=20
static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q)
{
- XilinxSPIPS *s =3D &q->parent_obj;
-
- if ((q->mmio_execution_enabled) && (q->lqspi_cached_addr !=3D ~0ULL)) {
- /* Invalidate the current mapped mmio */
- memory_region_invalidate_mmio_ptr(&s->mmlqspi, q->lqspi_cached_add=
r,
- LQSPI_CACHE_SIZE);
- }
-
q->lqspi_cached_addr =3D ~0ULL;
}
=20
@@ -1207,23 +1199,6 @@ static void lqspi_load_cache(void *opaque, hwaddr ad=
dr)
}
}
=20
-static void *lqspi_request_mmio_ptr(void *opaque, hwaddr addr, unsigned *s=
ize,
- unsigned *offset)
-{
- XilinxQSPIPS *q =3D opaque;
- hwaddr offset_within_the_region;
-
- if (!q->mmio_execution_enabled) {
- return NULL;
- }
-
- offset_within_the_region =3D addr & ~(LQSPI_CACHE_SIZE - 1);
- lqspi_load_cache(opaque, offset_within_the_region);
- *size =3D LQSPI_CACHE_SIZE;
- *offset =3D offset_within_the_region;
- return q->lqspi_buf;
-}
-
static uint64_t
lqspi_read(void *opaque, hwaddr addr, unsigned int size)
{
@@ -1245,7 +1220,6 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int si=
ze)
=20
static const MemoryRegionOps lqspi_ops =3D {
.read =3D lqspi_read,
- .request_ptr =3D lqspi_request_mmio_ptr,
.endianness =3D DEVICE_NATIVE_ENDIAN,
.valid =3D {
.min_access_size =3D 1,
@@ -1322,15 +1296,6 @@ static void xilinx_qspips_realize(DeviceState *dev, =
Error **errp)
sysbus_init_mmio(sbd, &s->mmlqspi);
=20
q->lqspi_cached_addr =3D ~0ULL;
-
- /* mmio_execution breaks migration better aborting than having strange
- * bugs.
- */
- if (q->mmio_execution_enabled) {
- error_setg(&q->migration_blocker,
- "enabling mmio_execution breaks migration");
- migrate_add_blocker(q->migration_blocker, &error_fatal);
- }
}
=20
static void xlnx_zynqmp_qspips_realize(DeviceState *dev, Error **errp)
@@ -1427,16 +1392,6 @@ static Property xilinx_zynqmp_qspips_properties[] =
=3D {
DEFINE_PROP_END_OF_LIST(),
};
=20
-static Property xilinx_qspips_properties[] =3D {
- /* We had to turn this off for 2.10 as it is not compatible with migra=
tion.
- * It can be enabled but will prevent the device to be migrated.
- * This will go aways when a fix will be released.
- */
- DEFINE_PROP_BOOL("x-mmio-exec", XilinxQSPIPS, mmio_execution_enabled,
- false),
- DEFINE_PROP_END_OF_LIST(),
-};
-
static Property xilinx_spips_properties[] =3D {
DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1),
DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4),
@@ -1450,7 +1405,6 @@ static void xilinx_qspips_class_init(ObjectClass *kla=
ss, void * data)
XilinxSPIPSClass *xsc =3D XILINX_SPIPS_CLASS(klass);
=20
dc->realize =3D xilinx_qspips_realize;
- dc->props =3D xilinx_qspips_properties;
xsc->reg_ops =3D &qspips_ops;
xsc->rx_fifo_size =3D RXFF_A_Q;
xsc->tx_fifo_size =3D TXFF_A_Q;
--=20
2.18.0