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[65.96.174.46]) by smtp.gmail.com with ESMTPSA id s8-v6sm441653qtc.71.2018.08.19.11.17.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 19 Aug 2018 11:17:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=pC4kTGWmwsHwlhbMH5s5bNG1Z25PTUUUb9QU10craPw=; b=SR3EzFOeTdSCCcSa+Y0i4yily+uT4iViFRst9U4vYygR8DAmVK/qblXXKtfritleOq Z7BR7RE7oMp2C+Tl4V+O0DNb6rhFO49oduQQdIbB0wF3PbcYcakhWEsqixvE3J/WhBN/ X10IWRp9hw59HbdCHNNmYS4av2yYQOjRmh/83gveL/b0JrlMaokmDi/FPtV/zL0YuCPF wT1R5dF6jC70I3PY/M4Q+iC2UK9sTVFCK0RYqUjR+UrNQtoVMfqWF7dBloYutQCzUe7f 6G1EnkoPfAUgjayfEYOqP1VevhlBigPK4ou+Dxovsogt5g0RrrBo7gzZjKK0KZ6lLUAG f7wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=pC4kTGWmwsHwlhbMH5s5bNG1Z25PTUUUb9QU10craPw=; b=RwXvf0UFqk0hk0yrxAsgw9RSj6dp0gko/xUQADT0UMSSk6eSsQfVrbc8n8GJWY+uFT 2p3uNGSLNyT/BfeVGBdfP3absk5PmA4lIXvpqj6Xp8hA2tUeAUBmL9rKPPUUJ9twrvGm Kp55cJvIPtVhnG2xh1fiGKqbwvFMPjhEQNcK1lwp73wfFo0Hsur4MWW8ga/TuMWzktt4 2U/g/f2hHL5FBgxwlQbX4WQeI/AUKbgiU3J1ZOCMcP6LHDfuo7vTiLel2UIC6puXIwjl BJbVS2orsCW+HIABAJpfs6TnphBqBhrOQ4Z5wCN3GHx5yWWP0hsqdTtWfmMS9DzegItZ M+OQ== X-Gm-Message-State: AOUpUlHbaKi8poS3mztJRkBr7btuCaJJRzZ1o54nafZsf4fveeqCOUvM 004Q49KB6hggL6Tg6VPWwIs= X-Google-Smtp-Source: AA+uWPyevgGZYW+v07n2RkK2kzbtr5Oo5feWtAWvDzkDRYwtuN40SKO1iRxbHu8Q8EN0pj1W3S3gfg== X-Received: by 2002:a37:3891:: with SMTP id f139-v6mr39703332qka.177.1534702663544; Sun, 19 Aug 2018 11:17:43 -0700 (PDT) From: andrew@andrewoates.com To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, qemu-devel@nongnu.org Date: Sun, 19 Aug 2018 14:17:25 -0400 Message-Id: <20180819181725.34098-1-andrew@andrewoates.com> X-Mailer: git-send-email 2.18.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH v2] target-i386: Fix lcall/ljmp to call gate in IA-32e mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Oates Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Andrew Oates Currently call gates are always treated as 32-bit gates. In IA-32e mode (either compatibility or 64-bit submode), system segment descriptors are always 64-bit. Treating them as 32-bit has the expected unfortunate effect: only the lower 32 bits of the offset are loaded, the stack pointer is truncated, a bad new stack pointer is loaded from the TSS (if switching privilege levels), etc. This change adds support for 64-bit call gate to the lcall and ljmp instructions. Additionally, there should be a check for non-canonical stack pointers, but I've omitted that since there doesn't seem to be checks for non-canonical addresses in this code elsewhere. I've left the raise_exception_err_ra lines unwapped at 80 columns to match the style in the rest of the file. Signed-off-by: Andrew Oates --- v2: fix ljmp as well, and generate #GP if ljmp/lcall'ing to a task gate or TSS segment. target/i386/seg_helper.c | 192 +++++++++++++++++++++++++++++++-------- 1 file changed, 152 insertions(+), 40 deletions(-) diff --git a/target/i386/seg_helper.c b/target/i386/seg_helper.c index 00301a0c04..b2adddcd7f 100644 --- a/target/i386/seg_helper.c +++ b/target/i386/seg_helper.c @@ -518,6 +518,11 @@ static void switch_tss(CPUX86State *env, int tss_selec= tor, =20 static inline unsigned int get_sp_mask(unsigned int e2) { +#ifdef TARGET_X86_64 + if (e2 & DESC_L_MASK) { + return 0; + } else +#endif if (e2 & DESC_B_MASK) { return 0xffffffff; } else { @@ -1640,6 +1645,14 @@ void helper_ljmp_protected(CPUX86State *env, int new= _cs, target_ulong new_eip, rpl =3D new_cs & 3; cpl =3D env->hflags & HF_CPL_MASK; type =3D (e2 >> DESC_TYPE_SHIFT) & 0xf; + +#ifdef TARGET_X86_64 + if (env->efer & MSR_EFER_LMA) { + if (type !=3D 12) { + raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, G= ETPC()); + } + } +#endif switch (type) { case 1: /* 286 TSS */ case 9: /* 386 TSS */ @@ -1662,6 +1675,23 @@ void helper_ljmp_protected(CPUX86State *env, int new= _cs, target_ulong new_eip, if (type =3D=3D 12) { new_eip |=3D (e2 & 0xffff0000); } + +#ifdef TARGET_X86_64 + if (env->efer & MSR_EFER_LMA) { + /* load the upper 8 bytes of the 64-bit call gate */ + if (load_segment_ra(env, &e1, &e2, new_cs + 8, GETPC())) { + raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfff= c, + GETPC()); + } + type =3D (e2 >> DESC_TYPE_SHIFT) & 0x1f; + if (type !=3D 0) { + raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfff= c, + GETPC()); + } + new_eip |=3D ((target_ulong)e1) << 32; + } +#endif + if (load_segment_ra(env, &e1, &e2, gate_cs, GETPC()) !=3D 0) { raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, = GETPC()); } @@ -1675,11 +1705,22 @@ void helper_ljmp_protected(CPUX86State *env, int ne= w_cs, target_ulong new_eip, (!(e2 & DESC_C_MASK) && (dpl !=3D cpl))) { raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, = GETPC()); } +#ifdef TARGET_X86_64 + if (env->efer & MSR_EFER_LMA) { + if (!(e2 & DESC_L_MASK)) { + raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xff= fc, GETPC()); + } + if (e2 & DESC_B_MASK) { + raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xff= fc, GETPC()); + } + } +#endif if (!(e2 & DESC_P_MASK)) { raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, = GETPC()); } limit =3D get_seg_limit(e1, e2); - if (new_eip > limit) { + if (new_eip > limit && + (!(env->hflags & HF_LMA_MASK) || !(e2 & DESC_L_MASK))) { raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); } cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl, @@ -1724,12 +1765,12 @@ void helper_lcall_protected(CPUX86State *env, int n= ew_cs, target_ulong new_eip, int shift, target_ulong next_eip) { int new_stack, i; - uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count; - uint32_t ss =3D 0, ss_e1 =3D 0, ss_e2 =3D 0, sp, type, ss_dpl, sp_mask; + uint32_t e1, e2, cpl, dpl, rpl, selector, param_count; + uint32_t ss =3D 0, ss_e1 =3D 0, ss_e2 =3D 0, type, ss_dpl, sp_mask; uint32_t val, limit, old_sp_mask; - target_ulong ssp, old_ssp; + target_ulong ssp, old_ssp, offset, sp; =20 - LOG_PCALL("lcall %04x:%08x s=3D%d\n", new_cs, (uint32_t)new_eip, shift= ); + LOG_PCALL("lcall %04x:" TARGET_FMT_lx " s=3D%d\n", new_cs, new_eip, sh= ift); LOG_PCALL_STATE(CPU(x86_env_get_cpu(env))); if ((new_cs & 0xfffc) =3D=3D 0) { raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); @@ -1807,6 +1848,15 @@ void helper_lcall_protected(CPUX86State *env, int ne= w_cs, target_ulong new_eip, type =3D (e2 >> DESC_TYPE_SHIFT) & 0x1f; dpl =3D (e2 >> DESC_DPL_SHIFT) & 3; rpl =3D new_cs & 3; + +#ifdef TARGET_X86_64 + if (env->efer & MSR_EFER_LMA) { + if (type !=3D 12) { + raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, G= ETPC()); + } + } +#endif + switch (type) { case 1: /* available 286 TSS */ case 9: /* available 386 TSS */ @@ -1833,8 +1883,23 @@ void helper_lcall_protected(CPUX86State *env, int ne= w_cs, target_ulong new_eip, raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, GE= TPC()); } selector =3D e1 >> 16; - offset =3D (e2 & 0xffff0000) | (e1 & 0x0000ffff); param_count =3D e2 & 0x1f; + offset =3D (e2 & 0xffff0000) | (e1 & 0x0000ffff); +#ifdef TARGET_X86_64 + if (env->efer & MSR_EFER_LMA) { + /* load the upper 8 bytes of the 64-bit call gate */ + if (load_segment_ra(env, &e1, &e2, new_cs + 8, GETPC())) { + raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, + GETPC()); + } + type =3D (e2 >> DESC_TYPE_SHIFT) & 0x1f; + if (type !=3D 0) { + raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, + GETPC()); + } + offset |=3D ((target_ulong)e1) << 32; + } +#endif if ((selector & 0xfffc) =3D=3D 0) { raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); } @@ -1849,46 +1914,80 @@ void helper_lcall_protected(CPUX86State *env, int n= ew_cs, target_ulong new_eip, if (dpl > cpl) { raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GET= PC()); } +#ifdef TARGET_X86_64 + if (env->efer & MSR_EFER_LMA) { + if (!(e2 & DESC_L_MASK)) { + raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc,= GETPC()); + } + if (e2 & DESC_B_MASK) { + raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc,= GETPC()); + } + shift++; + } +#endif if (!(e2 & DESC_P_MASK)) { raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, G= ETPC()); } =20 if (!(e2 & DESC_C_MASK) && dpl < cpl) { /* to inner privilege */ - get_ss_esp_from_tss(env, &ss, &sp, dpl, GETPC()); - LOG_PCALL("new ss:esp=3D%04x:%08x param_count=3D%d env->regs[R= _ESP]=3D" - TARGET_FMT_lx "\n", ss, sp, param_count, - env->regs[R_ESP]); - if ((ss & 0xfffc) =3D=3D 0) { - raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC= ()); - } - if ((ss & 3) !=3D dpl) { - raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC= ()); - } - if (load_segment_ra(env, &ss_e1, &ss_e2, ss, GETPC()) !=3D 0) { - raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC= ()); - } - ss_dpl =3D (ss_e2 >> DESC_DPL_SHIFT) & 3; - if (ss_dpl !=3D dpl) { - raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC= ()); - } - if (!(ss_e2 & DESC_S_MASK) || - (ss_e2 & DESC_CS_MASK) || - !(ss_e2 & DESC_W_MASK)) { - raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC= ()); - } - if (!(ss_e2 & DESC_P_MASK)) { - raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC= ()); +#ifdef TARGET_X86_64 + if (shift =3D=3D 2) { + sp =3D get_rsp_from_tss(env, dpl); + ss =3D dpl; /* SS =3D NULL selector with RPL =3D new CPL = */ + new_stack =3D 1; + sp_mask =3D 0; + ssp =3D 0; /* SS base is always zero in IA-32e mode */ + LOG_PCALL("new ss:rsp=3D%04x:%016llx env->regs[R_ESP]=3D" + TARGET_FMT_lx "\n", ss, sp, env->regs[R_ESP]); + } else +#endif + { + uint32_t sp32; + get_ss_esp_from_tss(env, &ss, &sp32, dpl, GETPC()); + LOG_PCALL("new ss:esp=3D%04x:%08x param_count=3D%d env->re= gs[R_ESP]=3D" + TARGET_FMT_lx "\n", ss, sp32, param_count, + env->regs[R_ESP]); + sp =3D sp32; + if ((ss & 0xfffc) =3D=3D 0) { + raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, G= ETPC()); + } + if ((ss & 3) !=3D dpl) { + raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, G= ETPC()); + } + if (load_segment_ra(env, &ss_e1, &ss_e2, ss, GETPC()) !=3D= 0) { + raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, G= ETPC()); + } + ss_dpl =3D (ss_e2 >> DESC_DPL_SHIFT) & 3; + if (ss_dpl !=3D dpl) { + raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, G= ETPC()); + } + if (!(ss_e2 & DESC_S_MASK) || + (ss_e2 & DESC_CS_MASK) || + !(ss_e2 & DESC_W_MASK)) { + raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, G= ETPC()); + } + if (!(ss_e2 & DESC_P_MASK)) { + raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, G= ETPC()); + } + + sp_mask =3D get_sp_mask(ss_e2); + ssp =3D get_seg_base(ss_e1, ss_e2); } =20 /* push_size =3D ((param_count * 2) + 8) << shift; */ =20 old_sp_mask =3D get_sp_mask(env->segs[R_SS].flags); old_ssp =3D env->segs[R_SS].base; - - sp_mask =3D get_sp_mask(ss_e2); - ssp =3D get_seg_base(ss_e1, ss_e2); - if (shift) { +#ifdef TARGET_X86_64 + if (shift =3D=3D 2) { + /* XXX: verify if new stack address is canonical */ + PUSHQ_RA(sp, env->segs[R_SS].selector, GETPC()); + PUSHQ_RA(sp, env->regs[R_ESP], GETPC()); + /* parameters aren't supported for 64-bit call gates */ + } else +#endif + if (shift =3D=3D 1) { PUSHL_RA(ssp, sp, sp_mask, env->segs[R_SS].selector, GETPC= ()); PUSHL_RA(ssp, sp, sp_mask, env->regs[R_ESP], GETPC()); for (i =3D param_count - 1; i >=3D 0; i--) { @@ -1917,7 +2016,13 @@ void helper_lcall_protected(CPUX86State *env, int ne= w_cs, target_ulong new_eip, new_stack =3D 0; } =20 - if (shift) { +#ifdef TARGET_X86_64 + if (shift =3D=3D 2) { + PUSHQ_RA(sp, env->segs[R_CS].selector, GETPC()); + PUSHQ_RA(sp, next_eip, GETPC()); + } else +#endif + if (shift =3D=3D 1) { PUSHL_RA(ssp, sp, sp_mask, env->segs[R_CS].selector, GETPC()); PUSHL_RA(ssp, sp, sp_mask, next_eip, GETPC()); } else { @@ -1928,11 +2033,18 @@ void helper_lcall_protected(CPUX86State *env, int n= ew_cs, target_ulong new_eip, /* from this point, not restartable */ =20 if (new_stack) { - ss =3D (ss & ~3) | dpl; - cpu_x86_load_seg_cache(env, R_SS, ss, - ssp, - get_seg_limit(ss_e1, ss_e2), - ss_e2); +#ifdef TARGET_X86_64 + if (shift =3D=3D 2) { + cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0); + } else +#endif + { + ss =3D (ss & ~3) | dpl; + cpu_x86_load_seg_cache(env, R_SS, ss, + ssp, + get_seg_limit(ss_e1, ss_e2), + ss_e2); + } } =20 selector =3D (selector & ~3) | dpl; --=20 2.18.0