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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id q85-v6sm9362783pfa.151.2018.08.18.12.01.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 18 Aug 2018 12:01:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3y2QWaXm15JxYeddyVGnwTp1qvTJ9/aMWE0lCIdt2XE=; b=XDkYfzhEbzjfZfWa+EJd4Eg8QvVambI15NeRAOoyTfbqM6BlsP2xnl7B1+Z6sqr+ZM Dw0yYou4Qe3afj3ru4nKqdqA2CIv0iwJ2ozrQ57iCDDCfanjsJqMv0C5gQomz/ccit/9 AqoCWmAJUxh62UXIKc3zvwugrHzIvUlnuqgZg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3y2QWaXm15JxYeddyVGnwTp1qvTJ9/aMWE0lCIdt2XE=; b=nvXyIy2COWyDzcYV3KN6zaWrwyTfpn97AjS0pBUV9d4/yKLhINlpGVjKW6JlwmPRlI p36VZwKQlQDB4Eko9ASCUIiZQnDG3Ku/nFy4+yA/abmDqbm/yw9O+CwykUFuRPLvw/Nb UULqVqthnChywJvFnWLWz3sdrY3bAk7zuBT5LY4StkZSXtDSEUBLuXJdKH30Oc0DuiDd 99zgPtSLCnoPaTJM54D/mPdaTD0nblVkHt+sSGPwtkdefNpBVofbRUFaQ36QvBz8DI2T 4t2ORqpcWTDX6CMGuDBsZ9OLeh9GyID05ItBLx44FDJwrHXMXtt+CNFoOMT5HwgwVeOC 9uRw== X-Gm-Message-State: AOUpUlEPgBlECQkJWxxNZ3OQkN0uNuyWlpSCUwd8/52b0JkFV/o4WIcf smNLOldVCHtIkipkt5/eaY4ZTjVryU4= X-Google-Smtp-Source: AA+uWPyu8x+lPjjLmtDzHCBo4vTufZ345EdveskzppY0x/SQx79as7f8VczUkiXKNQkQB9go4quCyQ== X-Received: by 2002:a62:4083:: with SMTP id f3-v6mr41769608pfd.229.1534618898628; Sat, 18 Aug 2018 12:01:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 18 Aug 2018 12:01:14 -0700 Message-Id: <20180818190118.12911-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180818190118.12911-1-richard.henderson@linaro.org> References: <20180818190118.12911-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v4 12/16] linux-user: Split out pread64, pwrite64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- linux-user/syscall.h | 45 +++++++++++++++++++++ linux-user/syscall-file.inc.c | 62 ++++++++++++++++++++++++++-- linux-user/syscall.c | 76 +++-------------------------------- linux-user/strace.list | 6 --- 4 files changed, 110 insertions(+), 79 deletions(-) diff --git a/linux-user/syscall.h b/linux-user/syscall.h index f84b40d742..1d4b7ea915 100644 --- a/linux-user/syscall.h +++ b/linux-user/syscall.h @@ -112,3 +112,48 @@ void print_syscall_ptr_ret(const SyscallDef *def, abi_= long ret); .name =3D #NAME, .args =3D args_##NAME, .impl =3D impl_##NAME, \ .arg_type =3D { __VA_ARGS__ } \ } + +/* + * Returns true if syscall NUM expects 64bit types aligned even + * on pairs of registers. + */ +static inline bool regpairs_aligned(void *cpu_env, int num) +{ +#ifdef TARGET_ARM + return ((CPUARMState *)cpu_env)->eabi; +#elif defined(TARGET_MIPS) && TARGET_ABI_BITS =3D=3D 32 + return true; +#elif defined(TARGET_PPC) && !defined(TARGET_PPC64) + /* SysV AVI for PPC32 expects 64bit parameters to be passed on + * odd/even pairs of registers which translates to the same as + * we start with r3 as arg1 + */ + return true; +#elif defined(TARGET_SH4) + /* SH4 doesn't align register pairs, except for p{read,write}64 */ + switch (num) { + case TARGET_NR_pread64: + case TARGET_NR_pwrite64: + return true; + default: + return false; + } +#elif defined(TARGET_XTENSA) + return true; +#else + return false; +#endif +} + +static inline uint64_t target_offset64(abi_ulong word0, abi_ulong word1) +{ +#if TARGET_ABI_BITS =3D=3D 32 +# ifdef TARGET_WORDS_BIGENDIAN + return ((uint64_t)word0 << 32) | word1; +# else + return ((uint64_t)word1 << 32) | word0; +# endif +#else + return word0; +#endif +} diff --git a/linux-user/syscall-file.inc.c b/linux-user/syscall-file.inc.c index 7eb5b968e2..c75c5dea9e 100644 --- a/linux-user/syscall-file.inc.c +++ b/linux-user/syscall-file.inc.c @@ -323,6 +323,62 @@ SYSCALL_IMPL(openat) } SYSCALL_DEF(openat, ARG_ATDIRFD, ARG_STR, ARG_OPENFLAG, ARG_MODEFLAG); =20 +/* + * Both pread64 and pwrite64 merge args into a 64-bit offset, + * but the input registers and ordering are target specific. + */ +#if TARGET_ABI_BITS =3D=3D 32 +SYSCALL_ARGS(pread64_pwrite64) +{ + /* We have already assigned out[0-2]. */ + int off =3D regpairs_aligned(cpu_env, TARGET_NR_pread64); + out[3] =3D target_offset64(in[3 + off], in[4 + off]); + return def; +} +#else +#define args_pread64_pwrite64 NULL +#endif + +SYSCALL_IMPL(pread64) +{ + void *p =3D lock_user(VERIFY_WRITE, arg2, arg3, 0); + abi_long ret; + + if (!p) { + return -TARGET_EFAULT; + } + ret =3D get_errno(pread64(arg1, p, arg3, arg4)); + unlock_user(p, arg2, ret); + return ret; +} + +static const SyscallDef def_pread64 =3D { + .name =3D "pread64", + .args =3D args_pread64_pwrite64, + .impl =3D impl_pread64, + .arg_type =3D { ARG_DEC, ARG_PTR, ARG_DEC, ARG_DEC64 } +}; + +SYSCALL_IMPL(pwrite64) +{ + void *p =3D lock_user(VERIFY_READ, arg2, arg3, 0); + abi_long ret; + + if (!p) { + return -TARGET_EFAULT; + } + ret =3D get_errno(pwrite64(arg1, p, arg3, arg4)); + unlock_user(p, arg2, 0); + return ret; +} + +static const SyscallDef def_pwrite64 =3D { + .name =3D "pwrite64", + .args =3D args_pread64_pwrite64, + .impl =3D impl_pwrite64, + .arg_type =3D { ARG_DEC, ARG_PTR, ARG_DEC, ARG_DEC64 } +}; + /* * Both preadv and pwritev merge args 4/5 into a 64-bit offset. * Moreover, the parts are *always* in little-endian order. @@ -330,9 +386,9 @@ SYSCALL_DEF(openat, ARG_ATDIRFD, ARG_STR, ARG_OPENFLAG,= ARG_MODEFLAG); #if TARGET_ABI_BITS =3D=3D 32 SYSCALL_ARGS(preadv_pwritev) { - /* We have already assigned out[0-3]. */ - abi_ulong lo =3D in[4], hi =3D in[5]; - out[4] =3D ((hi << (TARGET_ABI_BITS - 1)) << 1) | lo; + /* We have already assigned out[0-2]. */ + abi_ulong lo =3D in[3], hi =3D in[4]; + out[3] =3D ((hi << (TARGET_ABI_BITS - 1)) << 1) | lo; return def; } #else diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 16824386fd..eb6c8465b7 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -718,38 +718,6 @@ static inline int next_free_host_timer(void) } #endif =20 -/* ARM EABI and MIPS expect 64bit types aligned even on pairs or registers= */ -#ifdef TARGET_ARM -static inline int regpairs_aligned(void *cpu_env, int num) -{ - return ((((CPUARMState *)cpu_env)->eabi) =3D=3D 1) ; -} -#elif defined(TARGET_MIPS) && (TARGET_ABI_BITS =3D=3D 32) -static inline int regpairs_aligned(void *cpu_env, int num) { return 1; } -#elif defined(TARGET_PPC) && !defined(TARGET_PPC64) -/* SysV AVI for PPC32 expects 64bit parameters to be passed on odd/even pa= irs - * of registers which translates to the same as ARM/MIPS, because we start= with - * r3 as arg1 */ -static inline int regpairs_aligned(void *cpu_env, int num) { return 1; } -#elif defined(TARGET_SH4) -/* SH4 doesn't align register pairs, except for p{read,write}64 */ -static inline int regpairs_aligned(void *cpu_env, int num) -{ - switch (num) { - case TARGET_NR_pread64: - case TARGET_NR_pwrite64: - return 1; - - default: - return 0; - } -} -#elif defined(TARGET_XTENSA) -static inline int regpairs_aligned(void *cpu_env, int num) { return 1; } -#else -static inline int regpairs_aligned(void *cpu_env, int num) { return 0; } -#endif - #define ERRNO_TABLE_SIZE 1200 =20 /* target_to_host_errno_table[] is initialized from @@ -7045,22 +7013,6 @@ void syscall_init(void) } } =20 -#if TARGET_ABI_BITS =3D=3D 32 -static inline uint64_t target_offset64(uint32_t word0, uint32_t word1) -{ -#ifdef TARGET_WORDS_BIGENDIAN - return ((uint64_t)word0 << 32) | word1; -#else - return ((uint64_t)word1 << 32) | word0; -#endif -} -#else /* TARGET_ABI_BITS =3D=3D 32 */ -static inline uint64_t target_offset64(uint64_t word0, uint64_t word1) -{ - return word0; -} -#endif /* TARGET_ABI_BITS !=3D 32 */ - #ifdef TARGET_NR_truncate64 static inline abi_long target_truncate64(void *cpu_env, const char *arg1, abi_long arg2, @@ -10232,28 +10184,6 @@ static abi_long do_syscall1(void *cpu_env, int num= , abi_long arg1, #else #error unreachable #endif -#endif -#ifdef TARGET_NR_pread64 - case TARGET_NR_pread64: - if (regpairs_aligned(cpu_env, num)) { - arg4 =3D arg5; - arg5 =3D arg6; - } - if (!(p =3D lock_user(VERIFY_WRITE, arg2, arg3, 0))) - return -TARGET_EFAULT; - ret =3D get_errno(pread64(arg1, p, arg3, target_offset64(arg4, arg= 5))); - unlock_user(p, arg2, ret); - return ret; - case TARGET_NR_pwrite64: - if (regpairs_aligned(cpu_env, num)) { - arg4 =3D arg5; - arg5 =3D arg6; - } - if (!(p =3D lock_user(VERIFY_READ, arg2, arg3, 1))) - return -TARGET_EFAULT; - ret =3D get_errno(pwrite64(arg1, p, arg3, target_offset64(arg4, ar= g5))); - unlock_user(p, arg2, 0); - return ret; #endif case TARGET_NR_getcwd: if (!(p =3D lock_user(VERIFY_WRITE, arg1, arg2, 0))) @@ -12067,6 +11997,12 @@ static const SyscallDef *syscall_table(int num) #ifdef TARGET_NR_open S(open); #endif +#ifdef TARGET_NR_pread64 + S(pread64); +#endif +#ifdef TARGET_NR_pwrite64 + S(pwrite64); +#endif #ifdef TARGET_NR_readlink S(readlink); #endif diff --git a/linux-user/strace.list b/linux-user/strace.list index f41b604c63..586eb55482 100644 --- a/linux-user/strace.list +++ b/linux-user/strace.list @@ -1025,9 +1025,6 @@ #ifdef TARGET_NR_prctl { TARGET_NR_prctl, "prctl" , NULL, NULL, NULL }, #endif -#ifdef TARGET_NR_pread64 -{ TARGET_NR_pread64, "pread64" , NULL, NULL, NULL }, -#endif #ifdef TARGET_NR_prlimit64 { TARGET_NR_prlimit64, "prlimit64" , NULL, NULL, NULL }, #endif @@ -1052,9 +1049,6 @@ #ifdef TARGET_NR_putpmsg { TARGET_NR_putpmsg, "putpmsg" , NULL, NULL, NULL }, #endif -#ifdef TARGET_NR_pwrite64 -{ TARGET_NR_pwrite64, "pwrite64" , NULL, NULL, NULL }, -#endif #ifdef TARGET_NR_query_module { TARGET_NR_query_module, "query_module" , NULL, NULL, NULL }, #endif --=20 2.17.1