From nobody Wed Nov 5 13:10:58 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534469791710102.83118087624473; Thu, 16 Aug 2018 18:36:31 -0700 (PDT) Received: from localhost ([::1]:58866 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fqTgg-0008Ap-H3 for importer@patchew.org; Thu, 16 Aug 2018 21:36:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48395) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fqTei-00058b-6m for qemu-devel@nongnu.org; Thu, 16 Aug 2018 21:34:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fqTeg-0006A5-65 for qemu-devel@nongnu.org; Thu, 16 Aug 2018 21:34:23 -0400 Received: from mx1.redhat.com ([209.132.183.28]:60550) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fqTef-000691-Kc for qemu-devel@nongnu.org; Thu, 16 Aug 2018 21:34:21 -0400 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id C6767A2021; Fri, 17 Aug 2018 01:34:20 +0000 (UTC) Received: from localhost (ovpn-116-57.gru2.redhat.com [10.97.116.57]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9921F10018F8; Fri, 17 Aug 2018 01:34:17 +0000 (UTC) From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org Date: Thu, 16 Aug 2018 22:33:55 -0300 Message-Id: <20180817013400.13353-4-ehabkost@redhat.com> In-Reply-To: <20180817013400.13353-1-ehabkost@redhat.com> References: <20180817013400.13353-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Fri, 17 Aug 2018 01:34:20 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 3/8] i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , "Michael S. Tsirkin" , Robert Hoo , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Robert Hoo Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as SPEC_CTRL. At present, mark CPUID_7_0_EDX_ARCH_CAPABILITIES unmigratable, per Paolo's comment. Signed-off-by: Robert Hoo Message-Id: <1530781798-183214-3-git-send-email-robert.hu@linux.intel.com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.h | 1 + target/i386/cpu.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index b5c6686fe2..878444755f 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -690,6 +690,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Ins= tructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulat= ion Single Precision */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ +#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/ #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypa= ss Disable */ =20 #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Predicti= on Barrier */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 723e02221e..2bf9fcc556 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1000,12 +1000,13 @@ static FeatureWordInfo feature_word_info[FEATURE_WO= RDS] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "spec-ctrl", NULL, - NULL, NULL, NULL, "ssbd", + NULL, "arch-capabilities", NULL, "ssbd", }, .cpuid_eax =3D 7, .cpuid_needs_ecx =3D true, .cpuid_ecx =3D 0, .cpuid_reg =3D R_EDX, .tcg_features =3D TCG_7_0_EDX_FEATURES, + .unmigratable_flags =3D CPUID_7_0_EDX_ARCH_CAPABILITIES, }, [FEAT_8000_0007_EDX] =3D { .feat_names =3D { --=20 2.18.0.rc1.1.g3f1ff2140