From nobody Fri Dec 19 04:28:46 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534426991868339.24080062582937; Thu, 16 Aug 2018 06:43:11 -0700 (PDT) Received: from localhost ([::1]:55688 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fqIYQ-00042Y-J5 for importer@patchew.org; Thu, 16 Aug 2018 09:43:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59059) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fqIQa-0000R7-2C for qemu-devel@nongnu.org; Thu, 16 Aug 2018 09:35:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fqIQZ-0001yu-96 for qemu-devel@nongnu.org; Thu, 16 Aug 2018 09:35:04 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44468) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fqIQZ-0001yS-1G for qemu-devel@nongnu.org; Thu, 16 Aug 2018 09:35:03 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fqIQY-00007x-5O for qemu-devel@nongnu.org; Thu, 16 Aug 2018 14:35:02 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 16 Aug 2018 14:34:27 +0100 Message-Id: <20180816133438.17061-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180816133438.17061-1-peter.maydell@linaro.org> References: <20180816133438.17061-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 19/30] aspeed_sdmc: Fix saved values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 From: Joel Stanley This fixes the intended protection of read-only values in the configuration register. They were being always set to zero by mistake. The read-only fields depend on the configured memory size of the system, so they cannot be fixed at compile time. The most straight forward option was to store them in the state structure. Signed-off-by: Joel Stanley Reviewed-by: C=C3=A9dric Le Goater Tested-by: C=C3=A9dric Le Goater Message-id: 20180807075757.7242-3-joel@jms.id.au Signed-off-by: Peter Maydell --- include/hw/misc/aspeed_sdmc.h | 1 + hw/misc/aspeed_sdmc.c | 27 ++++++++------------------- 2 files changed, 9 insertions(+), 19 deletions(-) diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h index 682f0f5d56d..e079c66a7d7 100644 --- a/include/hw/misc/aspeed_sdmc.h +++ b/include/hw/misc/aspeed_sdmc.h @@ -27,6 +27,7 @@ typedef struct AspeedSDMCState { uint32_t silicon_rev; uint32_t ram_bits; uint64_t ram_size; + uint32_t fixed_conf; =20 } AspeedSDMCState; =20 diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index 0df008e52a1..24fd4aee2d8 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -126,10 +126,12 @@ static void aspeed_sdmc_write(void *opaque, hwaddr ad= dr, uint64_t data, case AST2400_A0_SILICON_REV: case AST2400_A1_SILICON_REV: data &=3D ~ASPEED_SDMC_READONLY_MASK; + data |=3D s->fixed_conf; break; case AST2500_A0_SILICON_REV: case AST2500_A1_SILICON_REV: data &=3D ~ASPEED_SDMC_AST2500_READONLY_MASK; + data |=3D s->fixed_conf; break; default: g_assert_not_reached(); @@ -198,25 +200,7 @@ static void aspeed_sdmc_reset(DeviceState *dev) memset(s->regs, 0, sizeof(s->regs)); =20 /* Set ram size bit and defaults values */ - switch (s->silicon_rev) { - case AST2400_A0_SILICON_REV: - case AST2400_A1_SILICON_REV: - s->regs[R_CONF] |=3D - ASPEED_SDMC_VGA_COMPAT | - ASPEED_SDMC_DRAM_SIZE(s->ram_bits); - break; - - case AST2500_A0_SILICON_REV: - case AST2500_A1_SILICON_REV: - s->regs[R_CONF] |=3D - ASPEED_SDMC_HW_VERSION(1) | - ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | - ASPEED_SDMC_DRAM_SIZE(s->ram_bits); - break; - - default: - g_assert_not_reached(); - } + s->regs[R_CONF] =3D s->fixed_conf; } =20 static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) @@ -234,10 +218,15 @@ static void aspeed_sdmc_realize(DeviceState *dev, Err= or **errp) case AST2400_A0_SILICON_REV: case AST2400_A1_SILICON_REV: s->ram_bits =3D ast2400_rambits(s); + s->fixed_conf =3D ASPEED_SDMC_VGA_COMPAT | + ASPEED_SDMC_DRAM_SIZE(s->ram_bits); break; case AST2500_A0_SILICON_REV: case AST2500_A1_SILICON_REV: s->ram_bits =3D ast2500_rambits(s); + s->fixed_conf =3D ASPEED_SDMC_HW_VERSION(1) | + ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | + ASPEED_SDMC_DRAM_SIZE(s->ram_bits); break; default: g_assert_not_reached(); --=20 2.18.0