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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k64-v6sm45231497pfc.160.2018.08.15.19.54.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 15 Aug 2018 19:54:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4XT9TWmQ7Mm3nTEPbhj1uqZlWg1AdfWzugZWwXnH6SI=; b=A5CrMWYTURowKomeCNY/wHqATBD2yyZNSjsLPXRqvazU+/PepftMw5b88ZtXataJ6z 6k53/G29AS/5+ljgdj/eiWUAUFM0D+mbLfdgvlq0Q4p3OXTlZRSph4aLr3BnFYu/McrI IkSu83aotgsYCwKw9y9MConC2xL9tl0BDCZlk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4XT9TWmQ7Mm3nTEPbhj1uqZlWg1AdfWzugZWwXnH6SI=; b=KgRK54LqcPEI2ch6ZYBMoK97DAvb+gMYHgWomAR6kH3doE5yhPFcEzDcG525QpWMtp vWGXImnzBIACjl+Um+ZTFtmSRESarUrCA3UlMnqL2kDHG3pYfb3hssTfDrkEEz7MB+jW cUNKn9AWK88a/u9TWcXjvV68ZdGABF9mBeF2JqlOY9yJEX9ngRBv9fSlIKA2uLdhar3x zSd5WLW2gPWiYA0qa/GbHVJlk/VD2ZJir0ckD6cZnydVzJXGOf7kWRG+TYvrqPG5eeo3 lxRZ2fjLzSEhvmO/IBM0mpoLpGx/ZXdvMlaSPhKw6jWjA9rg/NGEwR6pM+pAanoX7zKh S4Fg== X-Gm-Message-State: AOUpUlGTPCrf6tiqLZRSFTwXep++i7OVCUpSitRK2H2PFYPh2z3qDzhe u2uZK9DzZiUm/5+5+X6nVtrcXLS2D48= X-Google-Smtp-Source: AA+uWPyKdhTOKMSzq4stf2I2q1oa+pzU+QEdoEiVfugqLy8EJqs8FyW6igU9ZPBioJx4sshVVj3y8w== X-Received: by 2002:a63:5815:: with SMTP id m21-v6mr26679146pgb.78.1534388100111; Wed, 15 Aug 2018 19:55:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 15 Aug 2018 19:54:51 -0700 Message-Id: <20180816025452.21358-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180816025452.21358-1-richard.henderson@linaro.org> References: <20180816025452.21358-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42c Subject: [Qemu-devel] [PATCH 4/5] target/arm: Convert to HAVE_CMPXCHG128 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- target/arm/helper-a64.c | 259 +++++++++++++++++++++------------------- 1 file changed, 133 insertions(+), 126 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 7f6ad3000b..6e4e1b8a19 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -30,6 +30,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "qemu/int128.h" +#include "qemu/atomic128.h" #include "tcg.h" #include "fpu/softfloat.h" #include /* For crc32 */ @@ -509,189 +510,195 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t v= al, uint32_t bytes) return crc32c(acc, buf, bytes) ^ 0xffffffff; } =20 -/* Returns 0 on success; 1 otherwise. */ -static uint64_t do_paired_cmpxchg64_le(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi, - bool parallel, uintptr_t ra) +uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, + uint64_t new_lo, uint64_t new_hi) { - Int128 oldv, cmpv, newv; + Int128 cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high= ); + Int128 newv =3D int128_make128(new_lo, new_hi); + Int128 oldv; + uintptr_t ra =3D GETPC(); + uint64_t o0, o1; bool success; =20 - cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); - newv =3D int128_make128(new_lo, new_hi); - - if (parallel) { -#ifndef CONFIG_ATOMIC128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); - oldv =3D helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, = ra); - success =3D int128_eq(oldv, cmpv); -#endif - } else { - uint64_t o0, o1; - #ifdef CONFIG_USER_ONLY - /* ??? Enforce alignment. */ - uint64_t *haddr =3D g2h(addr); + /* ??? Enforce alignment. */ + uint64_t *haddr =3D g2h(addr); =20 - helper_retaddr =3D ra; - o0 =3D ldq_le_p(haddr + 0); - o1 =3D ldq_le_p(haddr + 1); - oldv =3D int128_make128(o0, o1); + helper_retaddr =3D ra; + o0 =3D ldq_le_p(haddr + 0); + o1 =3D ldq_le_p(haddr + 1); + oldv =3D int128_make128(o0, o1); =20 - success =3D int128_eq(oldv, cmpv); - if (success) { - stq_le_p(haddr + 0, int128_getlo(newv)); - stq_le_p(haddr + 1, int128_gethi(newv)); - } - helper_retaddr =3D 0; -#else - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi0 =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); - TCGMemOpIdx oi1 =3D make_memop_idx(MO_LEQ, mem_idx); - - o0 =3D helper_le_ldq_mmu(env, addr + 0, oi0, ra); - o1 =3D helper_le_ldq_mmu(env, addr + 8, oi1, ra); - oldv =3D int128_make128(o0, o1); - - success =3D int128_eq(oldv, cmpv); - if (success) { - helper_le_stq_mmu(env, addr + 0, int128_getlo(newv), oi1, ra); - helper_le_stq_mmu(env, addr + 8, int128_gethi(newv), oi1, ra); - } -#endif + success =3D int128_eq(oldv, cmpv); + if (success) { + stq_le_p(haddr + 0, int128_getlo(newv)); + stq_le_p(haddr + 1, int128_gethi(newv)); } + helper_retaddr =3D 0; +#else + int mem_idx =3D cpu_mmu_index(env, false); + TCGMemOpIdx oi0 =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); + TCGMemOpIdx oi1 =3D make_memop_idx(MO_LEQ, mem_idx); + + o0 =3D helper_le_ldq_mmu(env, addr + 0, oi0, ra); + o1 =3D helper_le_ldq_mmu(env, addr + 8, oi1, ra); + oldv =3D int128_make128(o0, o1); + + success =3D int128_eq(oldv, cmpv); + if (success) { + helper_le_stq_mmu(env, addr + 0, int128_getlo(newv), oi1, ra); + helper_le_stq_mmu(env, addr + 8, int128_gethi(newv), oi1, ra); + } +#endif =20 return !success; } =20 -uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t ne= w_hi) -{ - return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, false, GETPC(= )); -} - uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t a= ddr, uint64_t new_lo, uint64_t ne= w_hi) -{ - return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, true, GETPC()= ); -} - -static uint64_t do_paired_cmpxchg64_be(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi, - bool parallel, uintptr_t ra) { Int128 oldv, cmpv, newv; + uintptr_t ra =3D GETPC(); bool success; + int mem_idx; + TCGMemOpIdx oi; =20 - /* high and low need to be switched here because this is not actually a - * 128bit store but two doublewords stored consecutively - */ - cmpv =3D int128_make128(env->exclusive_high, env->exclusive_val); - newv =3D int128_make128(new_hi, new_lo); - - if (parallel) { -#ifndef CONFIG_ATOMIC128 + if (!HAVE_CMPXCHG128) { cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); - oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, = ra); - success =3D int128_eq(oldv, cmpv); -#endif - } else { - uint64_t o0, o1; - -#ifdef CONFIG_USER_ONLY - /* ??? Enforce alignment. */ - uint64_t *haddr =3D g2h(addr); - - helper_retaddr =3D ra; - o1 =3D ldq_be_p(haddr + 0); - o0 =3D ldq_be_p(haddr + 1); - oldv =3D int128_make128(o0, o1); - - success =3D int128_eq(oldv, cmpv); - if (success) { - stq_be_p(haddr + 0, int128_gethi(newv)); - stq_be_p(haddr + 1, int128_getlo(newv)); - } - helper_retaddr =3D 0; -#else - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi0 =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); - TCGMemOpIdx oi1 =3D make_memop_idx(MO_BEQ, mem_idx); - - o1 =3D helper_be_ldq_mmu(env, addr + 0, oi0, ra); - o0 =3D helper_be_ldq_mmu(env, addr + 8, oi1, ra); - oldv =3D int128_make128(o0, o1); - - success =3D int128_eq(oldv, cmpv); - if (success) { - helper_be_stq_mmu(env, addr + 0, int128_gethi(newv), oi1, ra); - helper_be_stq_mmu(env, addr + 8, int128_getlo(newv), oi1, ra); - } -#endif } =20 + mem_idx =3D cpu_mmu_index(env, false); + oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); + + cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); + newv =3D int128_make128(new_lo, new_hi); + oldv =3D helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra); + + success =3D int128_eq(oldv, cmpv); return !success; } =20 uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, uint64_t new_lo, uint64_t new_hi) { - return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, false, GETPC(= )); + /* + * High and low need to be switched here because this is not actually a + * 128bit store but two doublewords stored consecutively + */ + Int128 cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high= ); + Int128 newv =3D int128_make128(new_lo, new_hi); + Int128 oldv; + uintptr_t ra =3D GETPC(); + uint64_t o0, o1; + bool success; + +#ifdef CONFIG_USER_ONLY + /* ??? Enforce alignment. */ + uint64_t *haddr =3D g2h(addr); + + helper_retaddr =3D ra; + o1 =3D ldq_be_p(haddr + 0); + o0 =3D ldq_be_p(haddr + 1); + oldv =3D int128_make128(o0, o1); + + success =3D int128_eq(oldv, cmpv); + if (success) { + stq_be_p(haddr + 0, int128_gethi(newv)); + stq_be_p(haddr + 1, int128_getlo(newv)); + } + helper_retaddr =3D 0; +#else + int mem_idx =3D cpu_mmu_index(env, false); + TCGMemOpIdx oi0 =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); + TCGMemOpIdx oi1 =3D make_memop_idx(MO_BEQ, mem_idx); + + o1 =3D helper_be_ldq_mmu(env, addr + 0, oi0, ra); + o0 =3D helper_be_ldq_mmu(env, addr + 8, oi1, ra); + oldv =3D int128_make128(o0, o1); + + success =3D int128_eq(oldv, cmpv); + if (success) { + helper_be_stq_mmu(env, addr + 0, int128_gethi(newv), oi1, ra); + helper_be_stq_mmu(env, addr + 8, int128_getlo(newv), oi1, ra); + } +#endif + + return !success; } =20 uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t a= ddr, - uint64_t new_lo, uint64_t new_hi) + uint64_t new_lo, uint64_t ne= w_hi) { - return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true, GETPC()= ); + Int128 oldv, cmpv, newv; + uintptr_t ra =3D GETPC(); + bool success; + int mem_idx; + TCGMemOpIdx oi; + + if (!HAVE_CMPXCHG128) { + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + } + + mem_idx =3D cpu_mmu_index(env, false); + oi =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); + + /* + * High and low need to be switched here because this is not actually a + * 128bit store but two doublewords stored consecutively + */ + cmpv =3D int128_make128(env->exclusive_high, env->exclusive_val); + newv =3D int128_make128(new_hi, new_lo); + oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); + + success =3D int128_eq(oldv, cmpv); + return !success; } =20 /* Writes back the old data into Rs. */ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, uint64_t new_lo, uint64_t new_hi) { - uintptr_t ra =3D GETPC(); -#ifndef CONFIG_ATOMIC128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else Int128 oldv, cmpv, newv; + uintptr_t ra =3D GETPC(); + int mem_idx; + TCGMemOpIdx oi; + + if (!HAVE_CMPXCHG128) { + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + } + + mem_idx =3D cpu_mmu_index(env, false); + oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); =20 cmpv =3D int128_make128(env->xregs[rs], env->xregs[rs + 1]); newv =3D int128_make128(new_lo, new_hi); - - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); oldv =3D helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra); =20 env->xregs[rs] =3D int128_getlo(oldv); env->xregs[rs + 1] =3D int128_gethi(oldv); -#endif } =20 void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, uint64_t new_hi, uint64_t new_lo) { - uintptr_t ra =3D GETPC(); -#ifndef CONFIG_ATOMIC128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else Int128 oldv, cmpv, newv; + uintptr_t ra =3D GETPC(); + int mem_idx; + TCGMemOpIdx oi; + + if (!HAVE_CMPXCHG128) { + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + } + + mem_idx =3D cpu_mmu_index(env, false); + oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); =20 cmpv =3D int128_make128(env->xregs[rs + 1], env->xregs[rs]); newv =3D int128_make128(new_lo, new_hi); - - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); =20 env->xregs[rs + 1] =3D int128_getlo(oldv); env->xregs[rs] =3D int128_gethi(oldv); -#endif } =20 /* --=20 2.17.1