From nobody Wed Apr 16 13:38:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534272243987793.5319399923575; Tue, 14 Aug 2018 11:44:03 -0700 (PDT) Received: from localhost ([::1]:45727 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpeIU-0007w0-Qf for importer@patchew.org; Tue, 14 Aug 2018 14:44:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52347) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpduq-0004PK-AJ for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:21:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpdti-0006Wb-73 for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:19:36 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44398) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpdth-0006SH-Gy for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:18:25 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpdtf-00078k-2O for qemu-devel@nongnu.org; Tue, 14 Aug 2018 19:18:23 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 19:17:35 +0100 Message-Id: <20180814181815.23348-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814181815.23348-1-peter.maydell@linaro.org> References: <20180814181815.23348-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 05/45] accel/tcg: Pass read access type through to io_readx() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 The io_readx() function needs to know whether the load it is doing is an MMU_DATA_LOAD or an MMU_INST_FETCH, so that it can pass the right value to the cpu_transaction_failed() function. Plumb this information through from the softmmu code. This is currently not often going to give the wrong answer, because usually instruction fetches go via get_page_addr_code(). However once we switch over to handling execution from non-RAM by creating single-insn TBs, the path for an insn fetch to generate a bus error will be through cpu_ld*_code() and io_readx(), so without this change we will generate a d-side fault when we should generate an i-side fault. We also have to pass the access type via a CPU struct global down to unassigned_mem_read(), for the benefit of the targets which still use the cpu_unassigned_access() hook (m68k, mips, sparc, xtensa). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: C=C3=A9dric Le Goater Message-id: 20180710160013.26559-2-peter.maydell@linaro.org --- accel/tcg/softmmu_template.h | 11 +++++++---- include/qom/cpu.h | 6 ++++++ accel/tcg/cputlb.c | 5 +++-- memory.c | 3 ++- 4 files changed, 18 insertions(+), 7 deletions(-) diff --git a/accel/tcg/softmmu_template.h b/accel/tcg/softmmu_template.h index badbf148803..f060a693d41 100644 --- a/accel/tcg/softmmu_template.h +++ b/accel/tcg/softmmu_template.h @@ -99,11 +99,12 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchSt= ate *env, size_t mmu_idx, size_t index, target_ulong addr, uintptr_t retaddr, - bool recheck) + bool recheck, + MMUAccessType access_type) { CPUIOTLBEntry *iotlbentry =3D &env->iotlb[mmu_idx][index]; return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, recheck, - DATA_SIZE); + access_type, DATA_SIZE); } #endif =20 @@ -140,7 +141,8 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_u= long addr, /* ??? Note that the io helpers always read data in the target byte ordering. We should push the LE/BE request down into io. = */ res =3D glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr, - tlb_addr & TLB_RECHECK); + tlb_addr & TLB_RECHECK, + READ_ACCESS_TYPE); res =3D TGT_LE(res); return res; } @@ -207,7 +209,8 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_u= long addr, /* ??? Note that the io helpers always read data in the target byte ordering. We should push the LE/BE request down into io. = */ res =3D glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr, - tlb_addr & TLB_RECHECK); + tlb_addr & TLB_RECHECK, + READ_ACCESS_TYPE); res =3D TGT_BE(res); return res; } diff --git a/include/qom/cpu.h b/include/qom/cpu.h index bd796579ee4..ecf6ed556a9 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -386,6 +386,12 @@ struct CPUState { */ uintptr_t mem_io_pc; vaddr mem_io_vaddr; + /* + * This is only needed for the legacy cpu_unassigned_access() hook; + * when all targets using it have been converted to use + * cpu_transaction_failed() instead it can be removed. + */ + MMUAccessType mem_io_access_type; =20 int kvm_fd; struct KVMState *kvm_state; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 563fa30117e..51b1193044c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -789,7 +789,7 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail= (void *ptr) static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, target_ulong addr, uintptr_t retaddr, - bool recheck, int size) + bool recheck, MMUAccessType access_type, int size) { CPUState *cpu =3D ENV_GET_CPU(env); hwaddr mr_offset; @@ -831,6 +831,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEnt= ry *iotlbentry, } =20 cpu->mem_io_vaddr =3D addr; + cpu->mem_io_access_type =3D access_type; =20 if (mr->global_locking && !qemu_mutex_iothread_locked()) { qemu_mutex_lock_iothread(); @@ -843,7 +844,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEnt= ry *iotlbentry, section->offset_within_address_space - section->offset_within_region; =20 - cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_LOAD, + cpu_transaction_failed(cpu, physaddr, addr, size, access_type, mmu_idx, iotlbentry->attrs, r, retaddr); } if (locked) { diff --git a/memory.c b/memory.c index e9cd4469688..2ea16e7bfb0 100644 --- a/memory.c +++ b/memory.c @@ -1249,7 +1249,8 @@ static uint64_t unassigned_mem_read(void *opaque, hwa= ddr addr, printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); #endif if (current_cpu !=3D NULL) { - cpu_unassigned_access(current_cpu, addr, false, false, 0, size); + bool is_exec =3D current_cpu->mem_io_access_type =3D=3D MMU_INST_F= ETCH; + cpu_unassigned_access(current_cpu, addr, false, is_exec, 0, size); } return 0; } --=20 2.18.0