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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 04/45] nvic: Change NVIC to support ARMv6-M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Julia Suvorova The differences from ARMv7-M NVIC are: * ARMv6-M only supports up to 32 external interrupts (configurable feature already). The ICTR is reserved. * Active Bit Register is reserved. * ARMv6-M supports 4 priority levels against 256 in ARMv7-M. Signed-off-by: Julia Suvorova Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/intc/armv7m_nvic.h | 1 + hw/intc/armv7m_nvic.c | 21 ++++++++++++++++++--- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 8bc29112e3a..a472c9b8f05 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -57,6 +57,7 @@ typedef struct NVICState { VecInfo sec_vectors[NVIC_INTERNAL_VECTORS]; /* The PRIGROUP field in AIRCR is banked */ uint32_t prigroup[M_REG_NUM_BANKS]; + uint8_t num_prio_bits; =20 /* v8M NVIC_ITNS state (stored as a bool per bit) */ bool itns[NVIC_MAX_VECTORS]; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 49e8e2b94d4..351b69ab40b 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -420,6 +420,8 @@ static void set_prio(NVICState *s, unsigned irq, bool s= ecure, uint8_t prio) assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */ assert(irq < s->num_irq); =20 + prio &=3D MAKE_64BIT_MASK(8 - s->num_prio_bits, s->num_prio_bits); + if (secure) { assert(exc_is_banked(irq)); s->sec_vectors[irq].prio =3D prio; @@ -779,6 +781,9 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offse= t, MemTxAttrs attrs) =20 switch (offset) { case 4: /* Interrupt Control Type. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { + goto bad_offset; + } return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1; case 0xc: /* CPPWR */ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { @@ -1278,9 +1283,12 @@ static void nvic_writel(NVICState *s, uint32_t offse= t, uint32_t value, "Setting VECTRESET when not in DEBUG mode " "is UNPREDICTABLE\n"); } - s->prigroup[attrs.secure] =3D extract32(value, - R_V7M_AIRCR_PRIGROUP_SHI= FT, - R_V7M_AIRCR_PRIGROUP_LEN= GTH); + if (arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + s->prigroup[attrs.secure] =3D + extract32(value, + R_V7M_AIRCR_PRIGROUP_SHIFT, + R_V7M_AIRCR_PRIGROUP_LENGTH); + } if (attrs.secure) { /* These bits are only writable by secure */ cpu->env.v7m.aircr =3D value & @@ -1791,6 +1799,11 @@ static MemTxResult nvic_sysreg_read(void *opaque, hw= addr addr, break; case 0x300 ... 0x33f: /* NVIC Active */ val =3D 0; + + if (!arm_feature(&s->cpu->env, ARM_FEATURE_V7)) { + break; + } + startvec =3D 8 * (offset - 0x300) + NVIC_FIRST_IRQ; /* vector # */ =20 for (i =3D 0, end =3D size * 8; i < end && startvec + i < s->num_i= rq; i++) { @@ -2260,6 +2273,8 @@ static void armv7m_nvic_realize(DeviceState *dev, Err= or **errp) /* include space for internal exception vectors */ s->num_irq +=3D NVIC_FIRST_IRQ; =20 + s->num_prio_bits =3D arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2; + object_property_set_bool(OBJECT(&s->systick[M_REG_NS]), true, "realized", &err); if (err !=3D NULL) { --=20 2.18.0