From nobody Wed Apr 16 13:38:52 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534273422964850.0619988903867; Tue, 14 Aug 2018 12:03:42 -0700 (PDT) Received: from localhost ([::1]:45845 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpebV-0006Op-TN for importer@patchew.org; Tue, 14 Aug 2018 15:03:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52868) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpdvq-0005EL-QJ for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:22:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpduL-0006sK-BQ for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:20:38 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44432) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpduL-0006qy-31 for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:19:05 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpduJ-0007P9-2J for qemu-devel@nongnu.org; Tue, 14 Aug 2018 19:19:03 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 19:18:11 +0100 Message-Id: <20180814181815.23348-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814181815.23348-1-peter.maydell@linaro.org> References: <20180814181815.23348-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 41/45] target/arm: Implement tailchaining for M profile cores X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Tailchaining is an optimization in handling of exception return for M-profile cores: if we are about to pop the exception stack for an exception return, but there is a pending exception which is higher priority than the priority we are returning to, then instead of unstacking and then immediately taking the exception and stacking registers again, we can chain to the pending exception without unstacking and stacking. For v6M and v7M it is IMPDEF whether tailchaining happens for pending exceptions; for v8M this is architecturally required. Implement it in QEMU for all M-profile cores, since in practice v6M and v7M hardware implementations generally do have it. (We were already doing tailchaining for derived exceptions which happened during exception return, like the validity checks and stack access failures; these have always been required to be tailchained for all versions of the architecture.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20180720145647.8810-5-peter.maydell@linaro.org --- target/arm/helper.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 559065131a4..8b07bf214ec 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7162,6 +7162,22 @@ static void do_v7m_exception_exit(ARMCPU *cpu) return; } =20 + /* + * Tailchaining: if there is currently a pending exception that + * is high enough priority to preempt execution at the level we're + * about to return to, then just directly take that exception now, + * avoiding an unstack-and-then-stack. Note that now we have + * deactivated the previous exception by calling armv7m_nvic_complete_= irq() + * our current execution priority is already the execution priority we= are + * returning to -- none of the state we would unstack or set based on + * the EXCRET value affects it. + */ + if (armv7m_nvic_can_take_pending_exception(env->nvic)) { + qemu_log_mask(CPU_LOG_INT, "...tailchaining to pending exception\n= "); + v7m_exception_taken(cpu, excret, true, false); + return; + } + switch_v7m_security_state(env, return_to_secure); =20 { --=20 2.18.0