From nobody Sun Feb 8 19:30:37 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153427293921633.315877043250566; Tue, 14 Aug 2018 11:55:39 -0700 (PDT) Received: from localhost ([::1]:45791 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpeTe-00059t-8s for importer@patchew.org; Tue, 14 Aug 2018 14:55:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52785) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpdvj-00057z-78 for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:22:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpduE-0006np-Rw for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:20:31 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44426) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpduE-0006mZ-3u for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:18:58 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpduC-0007ME-Eg for qemu-devel@nongnu.org; Tue, 14 Aug 2018 19:18:56 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 19:18:04 +0100 Message-Id: <20180814181815.23348-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814181815.23348-1-peter.maydell@linaro.org> References: <20180814181815.23348-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 34/45] target/arm: Honour HCR_EL2.TGE and MDCR_EL2.TDE in debug register access checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some debug registers can be trapped via MDCR_EL2 bits TDRA, TDOSA, and TDA, which we implement in the functions access_tdra(), access_tdosa() and access_tda(). If MDCR_EL2.TDE or HCR_EL2.TGE are 1, the TDRA, TDOSA and TDA bits should behave as if they were 1. Implement this by having the access functions check MDCR_EL2.TDE and HCR_EL2.TGE. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20180724115950.17316-3-peter.maydell@linaro.org --- target/arm/helper.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 02c1c4d8404..3cd43cf7018 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -444,9 +444,11 @@ static CPAccessResult access_tdosa(CPUARMState *env, c= onst ARMCPRegInfo *ri, bool isread) { int el =3D arm_current_el(env); + bool mdcr_el2_tdosa =3D (env->cp15.mdcr_el2 & MDCR_TDOSA) || + (env->cp15.mdcr_el2 & MDCR_TDE) || + (env->cp15.hcr_el2 & HCR_TGE); =20 - if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA) - && !arm_is_secure_below_el3(env)) { + if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; } if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { @@ -462,9 +464,11 @@ static CPAccessResult access_tdra(CPUARMState *env, co= nst ARMCPRegInfo *ri, bool isread) { int el =3D arm_current_el(env); + bool mdcr_el2_tdra =3D (env->cp15.mdcr_el2 & MDCR_TDRA) || + (env->cp15.mdcr_el2 & MDCR_TDE) || + (env->cp15.hcr_el2 & HCR_TGE); =20 - if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA) - && !arm_is_secure_below_el3(env)) { + if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; } if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { @@ -480,9 +484,11 @@ static CPAccessResult access_tda(CPUARMState *env, con= st ARMCPRegInfo *ri, bool isread) { int el =3D arm_current_el(env); + bool mdcr_el2_tda =3D (env->cp15.mdcr_el2 & MDCR_TDA) || + (env->cp15.mdcr_el2 & MDCR_TDE) || + (env->cp15.hcr_el2 & HCR_TGE); =20 - if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA) - && !arm_is_secure_below_el3(env)) { + if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; } if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { --=20 2.18.0