From nobody Wed Apr 16 13:38:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534274017611168.97514181798385; Tue, 14 Aug 2018 12:13:37 -0700 (PDT) Received: from localhost ([::1]:45937 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpel1-00082Y-AO for importer@patchew.org; Tue, 14 Aug 2018 15:13:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52741) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpdvb-000510-Qm for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:22:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpduA-0006m3-QC for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:20:23 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44422) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpduA-0006kF-9r for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:18:54 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpdu8-0007Kj-3M for qemu-devel@nongnu.org; Tue, 14 Aug 2018 19:18:52 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 19:18:01 +0100 Message-Id: <20180814181815.23348-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814181815.23348-1-peter.maydell@linaro.org> References: <20180814181815.23348-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 31/45] arm/virt: Add support for GICv2 virtualization extensions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Luc Michel Add support for GICv2 virtualization extensions by mapping the necessary I/O regions and connecting the maintenance IRQ lines. Declare those additions in the device tree and in the ACPI tables. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell Message-id: 20180727095421.386-21-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- include/hw/arm/virt.h | 4 +++- hw/arm/virt-acpi-build.c | 6 +++-- hw/arm/virt.c | 52 +++++++++++++++++++++++++++++++++------- 3 files changed, 50 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 9a870ccb6a5..4cc57a7ef62 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -42,7 +42,7 @@ #define NUM_VIRTIO_TRANSPORTS 32 #define NUM_SMMU_IRQS 4 =20 -#define ARCH_GICV3_MAINT_IRQ 9 +#define ARCH_GIC_MAINT_IRQ 9 =20 #define ARCH_TIMER_VIRT_IRQ 11 #define ARCH_TIMER_S_EL1_IRQ 13 @@ -60,6 +60,8 @@ enum { VIRT_GIC_DIST, VIRT_GIC_CPU, VIRT_GIC_V2M, + VIRT_GIC_HYP, + VIRT_GIC_VCPU, VIRT_GIC_ITS, VIRT_GIC_REDIST, VIRT_GIC_REDIST2, diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 6ea47e25883..ce31abd62c2 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -659,6 +659,8 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) gicc->length =3D sizeof(*gicc); if (vms->gic_version =3D=3D 2) { gicc->base_address =3D cpu_to_le64(memmap[VIRT_GIC_CPU].base); + gicc->gich_base_address =3D cpu_to_le64(memmap[VIRT_GIC_HYP].b= ase); + gicc->gicv_base_address =3D cpu_to_le64(memmap[VIRT_GIC_VCPU].= base); } gicc->cpu_interface_number =3D cpu_to_le32(i); gicc->arm_mpidr =3D cpu_to_le64(armcpu->mp_affinity); @@ -668,8 +670,8 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { gicc->performance_interrupt =3D cpu_to_le32(PPI(VIRTUAL_PMU_IR= Q)); } - if (vms->virt && vms->gic_version =3D=3D 3) { - gicc->vgic_interrupt =3D cpu_to_le32(PPI(ARCH_GICV3_MAINT_IRQ)= ); + if (vms->virt) { + gicc->vgic_interrupt =3D cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ)); } } =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 281ddcdf6e2..0807be985c0 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -131,6 +131,8 @@ static const MemMapEntry a15memmap[] =3D { [VIRT_GIC_DIST] =3D { 0x08000000, 0x00010000 }, [VIRT_GIC_CPU] =3D { 0x08010000, 0x00010000 }, [VIRT_GIC_V2M] =3D { 0x08020000, 0x00001000 }, + [VIRT_GIC_HYP] =3D { 0x08030000, 0x00010000 }, + [VIRT_GIC_VCPU] =3D { 0x08040000, 0x00010000 }, /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ [VIRT_GIC_ITS] =3D { 0x08080000, 0x00020000 }, /* This redistributor space allows up to 2*64kB*123 CPUs */ @@ -440,18 +442,33 @@ static void fdt_add_gic_node(VirtMachineState *vms) =20 if (vms->virt) { qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", - GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV3_MAINT_= IRQ, + GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IR= Q, GIC_FDT_IRQ_FLAGS_LEVEL_HI); } } else { /* 'cortex-a15-gic' means 'GIC v2' */ qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "arm,cortex-a15-gic"); - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", - 2, vms->memmap[VIRT_GIC_DIST].base, - 2, vms->memmap[VIRT_GIC_DIST].size, - 2, vms->memmap[VIRT_GIC_CPU].base, - 2, vms->memmap[VIRT_GIC_CPU].size); + if (!vms->virt) { + qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + 2, vms->memmap[VIRT_GIC_DIST].bas= e, + 2, vms->memmap[VIRT_GIC_DIST].siz= e, + 2, vms->memmap[VIRT_GIC_CPU].base, + 2, vms->memmap[VIRT_GIC_CPU].size= ); + } else { + qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + 2, vms->memmap[VIRT_GIC_DIST].bas= e, + 2, vms->memmap[VIRT_GIC_DIST].siz= e, + 2, vms->memmap[VIRT_GIC_CPU].base, + 2, vms->memmap[VIRT_GIC_CPU].size, + 2, vms->memmap[VIRT_GIC_HYP].base, + 2, vms->memmap[VIRT_GIC_HYP].size, + 2, vms->memmap[VIRT_GIC_VCPU].bas= e, + 2, vms->memmap[VIRT_GIC_VCPU].siz= e); + qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", + GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IR= Q, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + } } =20 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle); @@ -573,6 +590,11 @@ static void create_gic(VirtMachineState *vms, qemu_irq= *pic) qdev_prop_set_uint32(gicdev, "redist-region-count[1]", MIN(smp_cpus - redist0_count, redist1_capacity)); } + } else { + if (!kvm_irqchip_in_kernel()) { + qdev_prop_set_bit(gicdev, "has-virtualization-extensions", + vms->virt); + } } qdev_init_nofail(gicdev); gicbusdev =3D SYS_BUS_DEVICE(gicdev); @@ -584,6 +606,10 @@ static void create_gic(VirtMachineState *vms, qemu_irq= *pic) } } else { sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); + if (vms->virt) { + sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); + sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); + } } =20 /* Wire the outputs from each CPU's generic timer and the GICv3 @@ -610,9 +636,17 @@ static void create_gic(VirtMachineState *vms, qemu_irq= *pic) ppibase + timer_irq[irq= ])); } =20 - qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",= 0, - qdev_get_gpio_in(gicdev, ppibase - + ARCH_GICV3_MAINT_IR= Q)); + if (type =3D=3D 3) { + qemu_irq irq =3D qdev_get_gpio_in(gicdev, + ppibase + ARCH_GIC_MAINT_IRQ); + qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interru= pt", + 0, irq); + } else if (vms->virt) { + qemu_irq irq =3D qdev_get_gpio_in(gicdev, + ppibase + ARCH_GIC_MAINT_IRQ); + sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); + } + qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, qdev_get_gpio_in(gicdev, ppibase + VIRTUAL_PMU_IRQ)); --=20 2.18.0