From nobody Wed Apr 16 13:37:41 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534272446837673.935715780043; Tue, 14 Aug 2018 11:47:26 -0700 (PDT) Received: from localhost ([::1]:45746 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpeLl-00045p-MS for importer@patchew.org; Tue, 14 Aug 2018 14:47:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52652) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpdvT-0004uI-VJ for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:21:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpdu5-0006ij-4g for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:20:15 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44416) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpdu4-0006gE-5x for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:18:48 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpdu2-0007I1-8y for qemu-devel@nongnu.org; Tue, 14 Aug 2018 19:18:46 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 19:17:55 +0100 Message-Id: <20180814181815.23348-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814181815.23348-1-peter.maydell@linaro.org> References: <20180814181815.23348-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 25/45] intc/arm_gic: Wire the vCPU interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Luc Michel Add the read/write functions to handle accesses to the vCPU interface. Those accesses are forwarded to the real CPU interface, with the CPU id being converted to the corresponding vCPU id (vCPU id =3D CPU id + GIC_NCPU). Signed-off-by: Luc Michel Message-id: 20180727095421.386-15-luc.michel@greensocs.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 37 +++++++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 0e1b23047e3..7ee2e6bcbb3 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1555,6 +1555,23 @@ static MemTxResult gic_do_cpu_write(void *opaque, hw= addr addr, return gic_cpu_write(s, id, addr, value, attrs); } =20 +static MemTxResult gic_thisvcpu_read(void *opaque, hwaddr addr, uint64_t *= data, + unsigned size, MemTxAttrs attrs) +{ + GICState *s =3D (GICState *)opaque; + + return gic_cpu_read(s, gic_get_current_vcpu(s), addr, data, attrs); +} + +static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + GICState *s =3D (GICState *)opaque; + + return gic_cpu_write(s, gic_get_current_vcpu(s), addr, value, attrs); +} + static const MemoryRegionOps gic_ops[2] =3D { { .read_with_attrs =3D gic_dist_read, @@ -1574,6 +1591,19 @@ static const MemoryRegionOps gic_cpu_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 +static const MemoryRegionOps gic_virt_ops[2] =3D { + { + .read_with_attrs =3D NULL, + .write_with_attrs =3D NULL, + .endianness =3D DEVICE_NATIVE_ENDIAN, + }, + { + .read_with_attrs =3D gic_thisvcpu_read, + .write_with_attrs =3D gic_thisvcpu_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + } +}; + static void arm_gic_realize(DeviceState *dev, Error **errp) { /* Device instance realize function for the GIC sysbus device */ @@ -1595,8 +1625,11 @@ static void arm_gic_realize(DeviceState *dev, Error = **errp) return; } =20 - /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ - gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, NULL); + /* This creates distributor, main CPU interface (s->cpuiomem[0]) and if + * enabled, virtualization extensions related interfaces (main virtual + * interface (s->vifaceiomem[0]) and virtual CPU interface). + */ + gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, gic_virt_ops); =20 /* Extra core-specific regions for the CPU interfaces. This is * necessary for "franken-GIC" implementations, for example on --=20 2.18.0