From nobody Wed Apr 16 13:41:15 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534273358971148.15887977623458; Tue, 14 Aug 2018 12:02:38 -0700 (PDT) Received: from localhost ([::1]:45839 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpeaT-0005VC-MI for importer@patchew.org; Tue, 14 Aug 2018 15:02:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52607) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpdvM-0004nu-5E for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:21:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpdu3-0006i0-WB for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:20:08 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44418) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpdu3-0006h8-81 for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:18:47 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpdu1-0007Hn-Ag for qemu-devel@nongnu.org; Tue, 14 Aug 2018 19:18:45 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 19:17:54 +0100 Message-Id: <20180814181815.23348-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814181815.23348-1-peter.maydell@linaro.org> References: <20180814181815.23348-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 24/45] intc/arm_gic: Implement virtualization extensions in gic_cpu_(read|write) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Luc Michel Implement virtualization extensions in the gic_cpu_read() and gic_cpu_write() functions. Those are the last bits missing to fully support virtualization extensions in the CPU interface path. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell Message-id: 20180727095421.386-14-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 3cddf658269..0e1b23047e3 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1401,9 +1401,12 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu= , int offset, case 0xd0: case 0xd4: case 0xd8: case 0xdc: { int regno =3D (offset - 0xd0) / 4; + int nr_aprs =3D gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; =20 - if (regno >=3D GIC_NR_APRS || s->revision !=3D 2) { + if (regno >=3D nr_aprs || s->revision !=3D 2) { *data =3D 0; + } else if (gic_is_vcpu(cpu)) { + *data =3D s->h_apr[gic_get_vcpu_real_id(cpu)]; } else if (gic_cpu_ns_access(s, cpu, attrs)) { /* NS view of GICC_APR is the top half of GIC_NSAPR */ *data =3D gic_apr_ns_view(s, regno, cpu); @@ -1417,7 +1420,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu,= int offset, int regno =3D (offset - 0xe0) / 4; =20 if (regno >=3D GIC_NR_APRS || s->revision !=3D 2 || !gic_has_group= s(s) || - gic_cpu_ns_access(s, cpu, attrs)) { + gic_cpu_ns_access(s, cpu, attrs) || gic_is_vcpu(cpu)) { *data =3D 0; } else { *data =3D s->nsapr[regno][cpu]; @@ -1452,7 +1455,8 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu= , int offset, s->abpr[cpu] =3D MAX(value & 0x7, GIC_MIN_ABPR); } } else { - s->bpr[cpu] =3D MAX(value & 0x7, GIC_MIN_BPR); + int min_bpr =3D gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_= BPR; + s->bpr[cpu] =3D MAX(value & 0x7, min_bpr); } break; case 0x10: /* End Of Interrupt */ @@ -1469,11 +1473,14 @@ static MemTxResult gic_cpu_write(GICState *s, int c= pu, int offset, case 0xd0: case 0xd4: case 0xd8: case 0xdc: { int regno =3D (offset - 0xd0) / 4; + int nr_aprs =3D gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; =20 - if (regno >=3D GIC_NR_APRS || s->revision !=3D 2) { + if (regno >=3D nr_aprs || s->revision !=3D 2) { return MEMTX_OK; } - if (gic_cpu_ns_access(s, cpu, attrs)) { + if (gic_is_vcpu(cpu)) { + s->h_apr[gic_get_vcpu_real_id(cpu)] =3D value; + } else if (gic_cpu_ns_access(s, cpu, attrs)) { /* NS view of GICC_APR is the top half of GIC_NSAPR */ gic_apr_write_ns_view(s, regno, cpu, value); } else { @@ -1488,6 +1495,9 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu= , int offset, if (regno >=3D GIC_NR_APRS || s->revision !=3D 2) { return MEMTX_OK; } + if (gic_is_vcpu(cpu)) { + return MEMTX_OK; + } if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { return MEMTX_OK; } --=20 2.18.0